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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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ST7LUS5 датащи(PDF) 67 Page - STMicroelectronics |
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ST7LUS5 датащи(HTML) 67 Page - STMicroelectronics |
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67 / 124 page  ST7LUS5, ST7LU05, ST7LU09 On-chip peripherals 67/124 Lite timer input capture register (LTICR) 10.2 12-bit autoreload timer (AT) 10.2.1 Introduction The 12-bit Autoreload Timer can be used for general-purpose timing functions. It is based on a free-running 12-bit up counter with a PWM output channel. 1WDGE Watchdog enable This bit is set and cleared by software. 0: Watchdog disabled 1: Watchdog enabled 0WDGD Watchdog Reset Delay This bit is set by software. It is cleared by hardware at the end of each tWDG period. 0: Watchdog reset not delayed 1: Watchdog reset delayed LTICR Reset value: 0000 0000 (00h) 7 654 32 10 ICR[7:0] RO Table 36. LTICR register description Bit Name Function 7:0 ICR[7:0] Input Capture Value These bits are read by software and cleared by hardware after a reset. If the ICF bit in the LTCSR is cleared, the value of the 8-bit up-counter will be captured when a rising or falling edge occurs on the LTIC pin. Table 35. LTCSR register description (continued) Bit Name Function Table 37. Lite timer register map and reset values Address (Hex.) Register label 7 6543210 0B LTCSR Reset value ICIE 0 ICF 0 TB 0 TBIE 0 TBF 0 WDGRF x WDGE 0 WDGD 0 0C LTICR Reset value ICR7 0 ICR6 0 ICR5 0 ICR4 0 ICR3 0 ICR2 0 ICR1 0 ICR0 0 |
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