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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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ST7LUS5 датащи(PDF) 78 Page - STMicroelectronics |
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ST7LUS5 датащи(HTML) 78 Page - STMicroelectronics |
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78 / 124 page  On-chip peripherals ST7LUS5, ST7LU05, ST7LU09 78/124 10.3.4 Low power modes Note: The A/D converter may be disabled by resetting the ADON bit. This feature allows reduced power consumption when no conversion is needed and between single shot conversions. 10.3.5 Interrupts None. 10.3.6 Register description Control/status register (ADCCSR) Table 47. Effect of low power modes on ADC Mode Description Wait No effect on A/D converter Halt A/D converter disabled After wake-up from Halt mode, the A/D converter requires a stabilization time tSTAB (see Electrical characteristics) before accurate conversions can be performed. ADCCSR Reset value: 0000 0000 (00h) 7 654 32 10 EOC SPEED ADON Reserved CH[2:0] RO R/W R/W - R/W Table 48. ADCCSR register description Bit Name Function 7EOC End of Conversion This bit is set by hardware. It is cleared by software reading the ADCDRH register. 0: Conversion is not complete 1: Conversion complete 6 SPEED ADC clock selection This bit is set and cleared by software. It is used together with the SLOW bit to configure the ADC clock speed. Refer to the table in the SLOW bit description. 5ADON A/D Converter on This bit is set and cleared by software. 0: A/D converter is switched off 1: A/D converter is switched on 4:3 - Reserved, must be kept cleared |
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