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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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ST7LUS5 датащи(PDF) 38 Page - STMicroelectronics |
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ST7LUS5 датащи(HTML) 38 Page - STMicroelectronics |
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38 / 124 page  Interrupts ST7LUS5, ST7LU05, ST7LU09 38/124 An external interrupt triggered on edge will be latched and the interrupt request automatically cleared upon entering the interrupt service routine. Caution: The type of sensitivity defined in the Miscellaneous or Interrupt register (if available) applies to the ei source. 7.3 Peripheral interrupts Different peripheral interrupt flags in the status register are able to cause an interrupt when they are active if both: ● The I bit of the CC register is cleared. ● The corresponding enable bit is set in the control register. If any of these two conditions is false, the interrupt is latched and thus remains pending. An interrupt request is cleared by doing one of the following: ● Writing ‘0’ to the corresponding bit in the status register ● Accessing the status register while the flag is set followed by a read or write of an associated register. Note: The clearing sequence resets the internal latch. A pending interrupt (that is, waiting for being enabled) will therefore be lost if the clear sequence is executed. Figure 13. Interrupt processing flowchart I BIT SET? Y N IRET? Y N FROM RESET LOAD PC FROM INTERRUPT VECTOR STACK PC, X, A, CC SET I BIT FETCH NEXT INSTRUCTION EXECUTE INSTRUCTION THIS CLEARS I BIT BY DEFAULT RESTORE PC, X, A, CC FROM STACK INTERRUPT Y N PENDING? |
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