AD4697BCPZ datasheet(27/107 Pages) AD

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Data Sheet

AD4697/AD4698

THEORY OF OPERATION

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Rev. 0 | 27 of 107

channel through SWMUX+ and SWMUX−. The acquisition phase ends

immediately at the beginning of the conversion phase.

The conversion phase is initiated by a rising edge on the CNV input

(in conversion mode only). When the conversion phase begins,

SW+, SW−, SWMUX+, and SWMUX− open first and sample the ana-

log input voltage on the capacitor arrays. The two capacitor arrays

are then disconnected from ADCIN+ and ADCIN− and connected

to REFGND. The sampled voltage is applied to the comparator

inputs, which causes the comparator to become unbalanced. The

ADC control logic performs a bit trial for each capacitor in the array,

starting with the MSB, by switching each element of the capacitor

array between REFGND and REF in sequence. During each bit

trial, the comparator input varies by binary weighted voltage steps

(VREF/2, VREF/4, …, VREF/65, 536), and the control logic acts to

bring the comparator back into a balanced condition. The state of

the comparator is recorded for each bit trial to produce the resulting

conversion result. The conversion phase terminates when all bit

trials are complete and the conversion result is ready.

The SAR ADC core generates one output code for each conversion

phase. Multiple output codes are averaged together to generate an

oversampled ADC result when the active channel is configured with

an OSR setting greater than 1 (see the Transfer Function section

and Oversampling and Decimation section).

The conversion time specification (tCONVERT) in Table 2 refers to the

delay between a CNV rising edge and the end of the conversion

phase. During the conversion phase, the ADC generates a busy

indicator to communicate to the digital host when a conversion is

complete and ready to be read via the SPI (see the Busy Indicator

section). When enabled, the busy indicator transitions high at the

start of the conversion phase, and transitions low at the end of the

conversion phase.

The delay between the end of each acquisition phase and the be-

ginning of the following acquisition phase depends on the channel

sequencing mode selected. When two-cycle command mode, the

standard sequencer, or the advanced sequencer are enabled, the

internal control logic determines the timing of the start of the next

acquisition phase. When single-cycle command mode is enabled,

the ADC core cannot enter the acquisition phase until the 5-bit

channel command is received over the SPI (see the Single-Cycle

Command Mode section).

The minimum acquisition time specification (tACQ) in Table 2 indi-

cates the minimum amount of time that the AD4697/AD4698 are in

the acquisition phase when running at the maximum sample rate.

When analog input high-Z mode is disabled, the switches that con-

nect the analog inputs to the capacitor arrays close immediately at

the start of the acquisition phase. When analog input high-Z mode

is enabled, these switches close partway through the acquisition

phase, but the resulting voltage kickback is significantly reduced.

As a result, the settling time and bandwidth requirements of the an-

alog front-end circuitry are reduced when analog input high-Z mode

is enabled (see Figure 21 and the Signal Settling Requirements

section).

The AD4697/AD4698 ADC core is controlled by an internal clock,

and the SPI serial clock (SCK) is not required for the conversion

process.

Figure 63. ADC Simplified Schematic

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