AD4697BCPZ datasheet(46/107 Pages) AD

46 / 107 page

Data Sheet

AD4697/AD4698

DIGITAL INTERFACE

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Rev. 0 | 46 of 107

ed, and the address decrements after each byte is accessed. When

the ADDR_DIR bit is set to 1, the ascending address option is

selected and the address increments after each byte is accessed.

The descending address option is selected by default.

Multibyte Register Access

Some AD4697/AD4698 configuration registers contain multiple

bytes of data stored in adjacent address locations in memory.

These registers are referred to as multibyte registers. The address

of each multibyte register is defined as the address of its least

significant byte, but the multibyte register contents extend across

multiple register addresses. For example, the STD_SEQ_CONFIG

significant byte is 0x024, and the address of its most significant

byte is 0x025. Table 31 specifies whether registers are single byte

or multibyte.

The state of the MB_STRICT bit in the SPI_CONFIG_C register

determines whether multibyte registers are treated as a single unit

of memory with one register address or as multiple registers that

are each one byte long with individual register addresses.

When the MB_STRICT bit is set to 0, each byte of a multibyte

the digital host to access one byte of a multibyte register without

accessing the other byte(s). With this setting, all data phases

in an SPI frame consist of a single byte rather than the entire

multibyte register, and each byte in a multibyte register is directly

addressable. The contents of either byte are updated by an SPI

write transaction as long as new data is provided for that entire

byte. Figure 85 and Figure 90 show examples where individual

bytes in a multibyte register (address = 0x0043) are accessed over

multiple SPI transactions in streaming mode and single instruction

mode with MB_STRICT = 0.

When the MB_STRICT bit is set to 1, all bytes of a multibyte

With this setting, the data phase includes all bytes when accessing

a multibyte register. If the digital host fails to read from or write to

the entire multibyte register, the SPI transaction is considered inva-

lid, and the MB_ERROR flag in the SPI_STATUS register is set to

1. This setting ensures that all modes or enable bits associated with

a multibyte register are updated simultaneously. The MB_STRICT

bit is set to 1 by default.

When the MB_STRICT bit is set to 1, the order in which each

byte of a multibyte register is read from or written to depends on

the selected address direction option (see the Address Direction

Options section). With the descending addresses option selected,

the first byte accessed in the data phase is the most significant byte

of the multibyte register, and each subsequent byte corresponds to

the data in the next lowest address. With the ascending addresses

option selected, the first byte accessed in the data phase is the

least significant byte of the multibyte register, and each subsequent

byte corresponds to the data in the next highest address. Figure 82

and Figure 83 show generalized read and write transactions of a

multibyte register for both address direction options.

When CRC is enabled, a checksum follows the data phase for

each SPI transaction. When the MB_STRICT bit is set to 0, the

checksum occurs after each byte of a multibyte register is accessed

(see Figure 85 and Figure 90). When the MB_STRICT bit is set to

1, the checksum only occurs after all bytes of the multibyte register

are accessed (see Figure 86 and Figure 91).

Figure 82. Multibyte Register Access with MB_STRICT = 1 and Descending Address

Figure 83. Multibyte Register Access with MB_STRICT = 1 and Ascending Address

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