AD4697BCPZ datasheet(49/107 Pages) AD

49 / 107 page

Data Sheet

AD4697/AD4698

DIGITAL INTERFACE

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Rev. 0 | 49 of 107

Figure 89. Single Instruction Mode SPI Frame

Figure 90. Single Instruction Mode SPI Frame, MB_STRICT = 0

Figure 91. Single Instruction Mode SPI Frame, MB_STRICT = 1, Descending Address

Figure 92. Single Instruction Mode SPI Frame, MB_STRICT = 1, Ascending Address

Checksum Protection

The AD4697/AD4698 include optional error checking based on

an 8-bit CRC in register configuration mode. When the CRC is

enabled, an 8-bit checksum code is appended to the data phase of

each register read or write transaction. The value of the checksum

is calculated from the data read or written over the SPI, and

therefore allows the AD4697/AD4698 and the digital host to detect

corrupted data. If the checksum does not match the corresponding

Figure 84 shows a generalized SPI frame for performing register

reads and writes with streaming mode selected, including the CRC

checksum. Figure 89 shows a generalized SPI frame for performing

including the CRC checksum. Note that the checksums on SDI

shown in both Figure 84 and Figure 89 are sent from the digital

host to the AD4697/AD4698, and the digital host must send a

valid checksum during the SPI read and write transactions pictured.

The only exception is when performing multiple register reads with

streaming mode selected, where the digital host is only required to

send a CRC on SDI for the first transaction (see Figure 84).

When the AD4697/AD4698 receive a checksum that does not

match their corresponding SPI transaction, the transaction is con-

sidered invalid, and the CRC_ERROR bit in the SPI_STATUS

(R/W1C) and must be written to 1 to be cleared.

When a write transaction is considered invalid, register contents

are not updated. When a read transaction is considered invalid, the

digital host must ignore the received register data and attempt the

when the register read transaction is considered valid (for example,

the HI_INn and LO_INn bits in the ALERT_STATUSn registers).

When streaming mode and the CRC are both enabled and an inva-

lid checksum is received for a given SPI transaction, all subsequent

SPI transactions are considered invalid for the remainder of the SPI

frame (until CS is brought high).

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