AD4697BCPZ datasheet(83/107 Pages) AD

83 / 107 page

Data Sheet

AD4697/AD4698

APPLICATIONS INFORMATION

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Rev. 0 | 83 of 107

On the WLCSP option, the busy indicator and alert indicator can be

output simultaneously on multiple general-purpose pins (see

Figure 125). In this configuration, the alert indicator can be used

to either gate the busy indicator or to act as an enable signal to

the host SPI peripheral while the busy indicator is still used to

synchronize SPI reads to the AD4698 internal conversion timing.

As described in the SPI Peripheral Synchronization in Conversion

Mode section, the digital host must complete the SPI frame before

the start of the next conversion. Refer to Figure 103 and the

Conversion Mode SPI Clock Frequency Requirements section for

guidelines on minimum SCK frequency and overall system latency

to achieve appropriate SPI transfer rates for the selected sample

rate.

Conversion Mode SPI Clock Frequency

Requirements

Conversion results for a given sample are available until the start of

the next conversion phase. The SCK frequency must therefore be

fast enough to read the data from the AD4697/AD4698 SPI before

the following CNV rising edge (or internal convert start signal when

autocycle mode is enabled).

The minimum required SCK frequency is a function of the sample

rate in use, the length of the SPI frame (in bits), and the serial

data output mode in use. Faster sample rates require faster SCK

frequencies because the time between conversions is shorter. Dual-

SDO mode and quad-SDO mode significantly reduce the required

SCK frequency for a given sample rate by doubling and quadrupling

the number of bits output on the SPI per SCK period, respectively

(see the Serial Data Output Modes section).

The number of SCK periods required per conversion mode frame

(NSCK) is a function of the number of bits per frame (NBITS) and the

number of serial data outputs (NSDO):

NSCK=NBITSNSDO

(21)

NBITS depends on the maximum OSR in use and whether the

status bits are enabled (see Table 21 and Table 22). NSDO is 1

for single-SDO mode, 2 for dual-SDO mode, and 4 for quad-SDO

mode. (Note that quad-SDO mode is only available on the WLCSP

option of the AD4698.)

The Conversion Mode Timing Diagrams section shows the timing

diagrams for the SPI frames in conversion mode. The start of the

conversion mode SPI frame must not occur before the tCONVERT

time has elapsed and must complete early enough to adhere to

the minimum tSCKCNV specification (see Table 2). Use the following

equation to calculate the amount of time available to complete an

SPI frame in conversion mode (tFRAME):

tFRAME=tCYC−tCONVERT−tSCKCNV= 1fCNV

−tCONVERT−tSCKCNV

(22)

where:

tCYC is the sample period.

tCONVERT is the maximum tCONVERT specification (see Table 2).

tSCKCNV is the SCK to CNV rising edge delay specification (see

Table 2).

fSCK is a function of tFRAME and NSCK as follows:

fSCK=NSCK/tFRAME

NBITS

NSDO× tCYC−tCONVERT−tSCKCNV

(23)

Table 28 shows examples of the minimum SCK frequency required

for several sample rates for each serial data output mode with

status bits disabled and enabled, and the OSR set to 1.

When single-cycle command mode is enabled, the multiplexer does

not update channels until the 5-bit channel command is clocked

in on SDI. The SCK frequency therefore impacts tACQ when single-

cycle command mode is enabled (see the Single-Cycle Command

Mode section).

When autocycle mode is enabled, tCYC is determined by the internal

convert start signal, the period of which is set by the AC_CYC bit

field, and the digital host must use either the busy indicator or the

alert indicator to synchronize the SPI frames with the internal con-

version timing (see the SPI Peripheral Synchronization in Autocycle

Mode section).

The digital host SPI peripheral may provide more SCK periods than

required per conversion mode SPI frame. The SDO behavior when

additional SCK falling edges occur after the LSB is clocked out

depends on the SDO_STATE bit setting. When SDO_STATE = 0,

SDO maintains its state when extra SCK falling edges occur. When

SDO_STATE = 1, SDO transitions to high impedance when extra

SCK falling edges occur.

Note that the minimum SCK period is longer for register configu-

ration mode than for conversion mode (see tSCK in Table 2). In

conversion mode, the minimum tSCK is 12.5 ns, corresponding to

a maximum fSCK of 80 MHz. In register configuration mode, the

minimum tSCK is 40 ns, corresponding to a maximum fSCK of 25

MHz. Therefore, for applications requiring conversion mode SCK

frequencies of greater than 25 MHz, ensure that the host SPI

peripheral serial clock rate is programmed accordingly while the

AD4697/AD4698 are in register configuration mode.

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