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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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AD4697BCPZ датащи(PDF) 14 Page - Analog Devices |
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AD4697BCPZ датащи(HTML) 14 Page - Analog Devices |
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14 / 107 page  Data Sheet AD4697/AD4698 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS analog.com Rev. 0 | 14 of 107 Table 8. AD4698 WLCSP Ball Function Descriptions Ball No. Mnemonic Type1 Description B1 SDO DO Serial Data Output. When the device is configured in register configuration mode, SDO is used to read the configuration register data during SPI read transactions. When the device is configured in conversion mode, SDO is used to read the conversion results. Data output is synchronized to the falling edge of SCK. B2 CNV DI Convert Input. When the device is configured in conversion mode, a rising edge on CNV initiates a conversion of the selected analog input. The AD4697/AD4698 can interface to a 4-wire SPI by tying CNV to CS. See the Digital Interface Operation section for more information. B3 REF AI Reference Input. VREF must be provided by an external precision reference voltage between 2.4 V and 5.1 V. The REF pin must be decoupled with a minimum 1 μF capacitor for optimal operation. See the Voltage Reference Input section for more information. B4 NC NC No Connect. Leave this pin open or connected to AGND. B5 IN0 AI Analog Input 0. B6 IN1 AI Analog Input 1. C1 GP2 DI/DO General-Purpose Pin 2. Can be configured to function as a general-purpose input/output, the threshold detection alert indicator, or the third serial data output in quad-SDO mode (see the General-Purpose Pins section). C2 SCK DI Serial Data Clock Input. SCK is used to clock out data on SDO and clock in data on SDI while the device is configured in either register configuration mode or conversion mode. C3 REFGND P Reference Ground. REF is referenced to REGND. IN0 to IN7 can be paired with REFGND to the ADC core to sample the differential voltage between them. See the Channel Configuration Options section for a detailed description on pairing inputs. C4 COM AI Common Channel Input. IN0 to IN7 can be paired with COM for the ADC core to sample the differential voltage between them. COM is nominally tied to signal ground (unipolar mode) or VREF/2 (pseudobipolar mode). See the Channel Configuration Options section for a detailed description on pairing inputs, unipolar mode, and pseudobipolar mode. C5 IN2 AI Analog Input 2. C6 IN3 AI Analog Input 3. D1 BSY_ALT_GP0 DI/DO General-Purpose Pin 0. On the WLCSP option, BSY_ALT_GP0 can be configured to function as a GPIO, the threshold detection alert indicator, or the busy indicator (see the General-Purpose Pins section). D2 GP1 DI/DO General-Purpose Pin 1. Can be configured to function as a general-purpose input/output, or the second serial data output in dual- and quad-SDO modes (see the General-Purpose Pins section). D3 RESET DI Hardware Reset Input. Drive RESET low to perform a hardware reset of the device and reset the register states to the default values (see the Device Reset section). D4 AGND P Analog Supply Ground. AVDD, LDO_IN, and VDD are referenced to AGND. D5 IN5 AI Analog Input 5. D6 IN4 AI Analog Input 4. E1 VIO P Input/Output Interface Digital Power. VIO is nominally the same supply as the host interface (for example, 1.2 V to 1.8 V). Decouple VIO to IOGND with a local 100 nF capacitor. E2 GP3 DI/DO General-Purpose Pin 3. Can be configured to function as a general-purpose input/output, the busy indicator, or the fourth serial data output in quad-SDO mode (see the General-Purpose Pins section). E3 IOGND P Input/Output Interface Digital Supply Ground. VIO is referenced to IOGND. E4 NC NC No Connect. Leave this pin open or connected to AGND. E5 NC NC No Connect. Leave this pin open or connected to AGND. E6 NC NC No Connect. Leave this pin open or connected to AGND. F1 VDD P ADC Core Power Supply. VDD is nominally 1.8 V. VDD must be decoupled with a local 100 nF capacitor to AGND. When the internal LDO is enabled, VDD is internally generated. Disable the internal LDO when supplying VDD from an external source. F2 LDO_IN P Internal LDO Input. LDO_IN is nominally 2.4 V to 5.5 V when the internal LDO is enabled. Decouple LDO_IN to AGND with a local 100 nF capacitor. If powering VDD with an external 1.8 V rail, tie LDO_IN to AGND. See the Internal LDO section for more information. F3 AVDD P Analog Power Supply. AVDD is nominally 3.15 V to 5.5 V. Decouple AVDD to AGND with a local 100 nF capacitor. F4 NC NC No Connect. Leave this pin open or connected to AGND. F5 IN7 AI Analog Input 7. F6 IN6 AI Analog Input 6. 1 DI is digital input, AI is analog input, NC is no internal connection, DO is digital output, and P is power. |
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