AD4697BCPZ datasheet(85/107 Pages) AD

85 / 107 page

Data Sheet

AD4697/AD4698

APPLICATIONS INFORMATION

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Rev. 0 | 85 of 107

single-cycle command modes, but because CYC_CTRL is in the

setup register, it can be configured in the same frame as the

SPI_MODE bit is set to put the device in conversion mode.

After the channel sequencing mode settings are configured, update

the CONFIG_INn register settings as needed to select the channel

configuration settings, including the threshold detection alert enable

setting, polarity mode, pin pairing option, the analog input high-Z

mode enable setting, and the OSR. When the standard sequencer

is enabled, the settings programmed into the CONFIG_INn register

bits are applied to all analog input channels. When any other chan-

nel sequencing mode is selected, the settings in each CONFIG_INn

Table 54 for a detailed description of the bits in the CONFIG_INn

registers.

When enabling threshold detection for any set of channels, update

the values in the corresponding UPPER_INn and LOWER_INn

registers to implement the desired upper and lower threshold limits

(see Table 55 and Table 56). The ALERT_MODE bit must be updat-

ed to enable or disable hysteresis, but because ALERT_MODE is

in the setup register, it can be configured in the same frame as

the SPI_MODE bit is set to put the device in conversion mode. If

enabling hysteresis, the HYST_INn registers must be updated to

implement the desired hysteresis settings.

If utilizing any of the general-purpose pin functions described in

the General-Purpose Pins section, update the GPIO_CTRL register

and GP_MODE register contents accordingly (see Table 50 and

Table 51).

If using autocycle mode, update the settings in the AC_CTRL regis-

ter to enable autocycle mode and select the desired sample rate

(see Table 48). Autocycle mode is disabled by default. Therefore, if

autocycle mode is not being used, it is not necessary to update the

AC_CTRL register after a device reset.

If utilizing offset and gain correction, update the settings in the

OFFSET_INn and GAIN_INn registers accordingly. If a calibration

routine is required to determine the necessary offset and gain

correction values for each channel, update the OFFSET_INn and

GAIN_INn registers after putting the AD4697/AD4698 into conver-

sion mode to collect enough conversion data.

After all other necessary configuration register settings have been

updated, put the AD4697/AD4698 in conversion mode by setting

the SPI_MODE bit in the setup register to 1. Ensure that all other

bits in the setup register are set to achieve the desired device

settings (see Table 45).

Prior to updating the setup register to put the device in conver-

sion mode, the digital host can optionally check the state of the

SPI_ERROR bit in the status register to verify that there were no

errors in updating the configuration registers. The host can also

check the state of the CLAMP_STATUS register to check if any

of the AD4697/AD4698 analog input channels are experiencing

overvoltage events prior to putting the device into conversion mode.

While the AD4697/AD4698 are in conversion mode, the SPI cannot

be used to update the configuration registers. If any of the configu-

ration registers must be read from or updated while the device is

already in conversion mode, send the register configuration mode

command during a conversion mode SPI frame to put the device

back into register configuration mode (see the Register Configura-

tion Mode Command section).

EFFECTIVE CHANNEL SAMPLE RATE

The AD4697/AD4698 analog inputs are multiplexed to a single ADC

core, and the state of the multiplexer is updated at the end of the

conversion phase. The effective sample rate for each channel in

the channel sequence is therefore some fraction of the sample rate

of the ADC, which is set by fCNV. The effective sample rate for a

channel is defined as the frequency at which each new conversion

result is generated for that channel.

For an analog input to have an effective sample rate, new results

must be generated at a constant rate for the entire channel se-

quence or at least for a long enough time span to perform the

necessary analysis. For example, to calculate an FFT and perform

ac analysis on the ADC data for a given channel, the sampling

interval between each sample gathered for that channel must be

constant. The effective sample rate for an analog input (fS_INx) is a

function of fCNV and the number of CNV periods between each time

it is sampled (NCNV). The following relationship applies for each of

the eight analog inputs (IN0 to IN7) and for the temperature sensor

as follows:

fS_INx=fCNVNCNV

(24)

The required fS_INx for each analog input is determined by its input

signal frequency range. The Nyquist frequency for a given analog

input (which is half of fS_INx) must be greater than the highest signal

frequency being measured to avoid aliasing.

When the standard sequencer is enabled, each enabled channel

in the STD_SEQ_CONFIG register is sampled once per sequence

iteration. fS_INx is therefore always constant for each enabled chan-

nel when the standard sequencer is enabled, and is calculated as

follows:

fS_INx= fCNVNEN×OSR

(25)

where:

NEN is the number of inputs included in the channel sequence

and can range from 1 (only one channel enabled) to 9 (when all

channels and the temperature sensor are enabled).

OSR is the oversampling ratio selected by the OSR_SET bit field in

the CONFIG_IN0 register.

In the example provided in Figure 76, with NEN = 4 and OSR =

1, fS_INx is fCNV/4. If the OSR is programmed to 4 in this example,

fS_INx is fCNV/16.

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