AD4697BCPZ datasheet(12/107 Pages) AD

12 / 107 page

Data Sheet

AD4697/AD4698

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

analog.com

Rev. 0 | 12 of 107

Figure 2. AD4697/AD4698 LFCSP Pin Configuration

Table 7. AD4697/AD4698 LFCSP Pin Function Descriptions

No.

Mnemonic.

Type1

Description

IN1

Analog Input 1.

IN2

Analog Input 2.

IN3

Analog Input 3.

COM

Common Channel Input. IN0 to IN7 can be paired with COM for the ADC core to sample the differential voltage between them. COM

is nominally tied to signal ground (unipolar mode) or VREF/2 (pseudobipolar mode). See the Channel Configuration Options section

for a detailed description on pairing inputs, unipolar mode, and pseudobipolar mode.

IN4

Analog Input 4.

IN5

Analog Input 5.

IN6

Analog Input 6.

IN7

Analog Input 7.

AGND

Analog Supply Ground. AVDD, LDO_IN, and VDD are referenced to AGND.

AVDD

Analog Power Supply. AVDD is nominally 3.15 V to 5.5 V. Decouple AVDD to AGND with a local 100 nF capacitor.

LDO_IN

Internal LDO Input. LDO_IN is nominally 2.4 V to 5.5 V when the internal LDO is enabled. Decouple LDO_IN to AGND with a

local 100 nF capacitor. If powering VDD with an external 1.8 V rail, tie LDO_IN to AGND. See the Internal LDO section for more

information.

VDD

ADC Core Power Supply. VDD is nominally 1.8 V. VDD must be decoupled with a local 100 nF capacitor to AGND. When the internal

LDO is enabled, VDD is internally generated. Disable the internal LDO when supplying VDD from an external source.

RESET

Hardware Reset Input. Drive RESET low to perform a hardware reset of the device and reset the register states to the default values

(see the Device Reset section).

VIO

Input/Output Interface Digital Power. VIO is nominally the same supply as the host interface (for example, 1.2 V to 1.8 V). Decouple

VIO to IOGND with a local 100 nF capacitor.

IOGND

Input/Output Interface Digital Supply Ground. VIO is referenced to IOGND.

BSY_ALT_GP0

DI/DO

General-Purpose Pin 0. On the LFCSP option, BSY_ALT_GP0 can be configured to function as a general-purpose input/output

(GPIO), the threshold detection alert indicator, the busy indicator, or the second serial data output in dual-SDO mode (see the

General-Purpose Pins section).

SDO

Serial Data Output. When the device is configured in register configuration mode, SDO is used to read the configuration register data

during SPI read transactions. When the device is configured in conversion mode, SDO is used to read the conversion results. Data

output is synchronized to the falling edge of SCK.

SCK

Serial Data Clock Input. SCK is used to clock out data on SDO and clock in data on SDI while the device is configured in either

SDI

Serial Data Input. When the device is configured in register configuration mode, SDI is used to perform SPI read and write

transactions to access the configuration registers. In conversion mode, SDI receives 5-bit commands from the digital host, as shown

in Table 18.

AD4697BCPZ датащи(PDF) 12 Page - Analog Devices

AD4697BCPZ датащи(HTML) 12 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL