EDBA164B4PK-1DITF-R datasheet(34/152 Pages) MICRON

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Table 16: MR1 Op-Code Bit Definitions (Continued)

Feature

Type

Definition

Notes

BT = burst type

Write-only

OP3

0b: Sequential (default)

1b: Interleaved

WC = wrap control

Write-only

OP4

0b: Wrap (default)

1b: No wrap (allowed for BL4 only)

nWR = number of tWR clock

cycles

Write-only

OP[7:5]

001b: nWR = 3 (default)

010b: nWR = 4

011b: nWR = 5

100b: nWR = 6

101b: nWR = 7

110b: nWR = 8

All others: Reserved

Notes:

1. BL16, interleaved is not an official combination to be supported.

2. The programmed value in nWR register is the number of clock cycles that determines

when to start internal precharge operation for a WRITE burst with AP enabled. It is de-

termined by RU (tWR/tCK).

Table 17: Burst Sequence by Burst Length (BL), Burst Type (BT), and Wrap Control (WC)

Notes 1–5 apply to all parameters and conditions

Burst Cycle Number and Burst Address Sequence

Any

Wrap

0123

2301

Any

wrap

yy +

y +

Seq

Wrap

01234567

23456701

45670123

67012345

Int

01234567

23016745

45670123

67452301

Any

wrap

Illegal (not supported)

216-Ball and 220-Ball, Dual-Channel LPDDR2 SDRAM

Mode Register Definition

09005aef85eb530a

216b_220b_2ch_2e0e_embedded_lpddr2.pdf – Rev. F 08 /16 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

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