EDBA164B4PK-1DITF-R datasheet(43/152 Pages) MICRON

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Figure 13: Command and Input Setup and Hold

Command

NOP

Command

CK_c

CK_t

CS_n

rise

CA[9:0]

CMD

Don’t Care

Transitioning data

fall

rise

fall

rise

fall

rise

fall

NOP

tIS tIH

IL(AC)

IH(DC)

IH(AC)

IL(DC)

Note:

1. Setup and hold conditions also apply to the CKE pin. For timing diagrams related to the

CKE pin, see the Power-Down section.

Figure 14: CKE Input Setup and Hold

Tx + 1

CK_c

CK_t

CKE

HIGH or LOW, but defined

tIHCKE

tISCKE

tIHCKE

tISCKE

IHCKE

ILCKE

Notes:

1. After CKE is registered LOW, the CKE signal level is maintained below VILCKE for tCKE

specification (LOW pulse width).

2. After CKE is registered HIGH, the CKE signal level is maintained below VIHCKE for tCKE

specification (HIGH pulse width).

ACTIVATE Command

The ACTIVATE command is issued by holding CS_n LOW, CA0 LOW, and CA1 HIGH at

the rising edge of the clock. The bank addresses BA[2:0] are used to select the desired

bank. Row addresses are used to determine which row to activate in the selected bank.

The ACTIVATE command must be applied before any READ or WRITE operation can be

executed. The device can accept a READ or WRITE command at tRCD after the ACTI-

VATE command is issued. After a bank has been activated, it must be precharged before

another ACTIVATE command can be applied to the same bank. The bank active and

precharge times are defined as tRAS and tRP, respectively. The minimum time interval

between successive ACTIVATE commands to the same bank is determined by the RAS

216-Ball and 220-Ball, Dual-Channel LPDDR2 SDRAM

ACTIVATE Command

09005aef85eb530a

216b_220b_2ch_2e0e_embedded_lpddr2.pdf – Rev. F 08 /16 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

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