EDBA164B4PK-1DITF-R datasheet(61/152 Pages) MICRON

61 / 152 page

Figure 38: WRITE Burst Followed by PRECHARGE – WL = 1, BL = 4

Bank n

col addr

Col addr

WRITE

NOP

Tx + 1

Ty + 1

CK_c

CK_t

CA[9:0]

CMD

DQS_c

DQS_t

WL = 1

tWR

Completion of burst WRITE

Transitioning data

NOP

PRECHARGE

tDQSSmax

NOP

IN A0

IN A1

IN A2

IN A3

ACTIVATE

NOP

Bank n

row addr

Row addr

DQS_c

DQS_t

tDQSSmin

≥tRP

IN A0

IN A1

IN A2

IN A3

Case 1: tDQSSmax

Case 2: tDQSSmin

Auto Precharge operation

Before a new row can be opened in an active bank, the active bank must be precharged

using either the PRECHARGE command or the auto precharge function. When a READ

or WRITE command is issued to the device, the auto precharge bit (AP) can be set to

enable the active bank to automatically begin precharge at the earliest possible mo-

ment during the burst READ or WRITE cycle.

If AP is LOW when the READ or WRITE command is issued, then normal READ or

WRITE burst operation is executed and the bank remains active at the completion of

the burst.

If AP is HIGH when the READ or WRITE command is issued, the auto precharge func-

tion is engaged. This feature enables the PRECHARGE operation to be partially or com-

pletely hidden during burst READ cycles (dependent upon READ or WRITE latency),

thus improving system performance for random data access.

READ Burst with Auto Precharge

If AP (CA0f ) is HIGH when a READ command is issued, the READ with auto precharge

function is engaged.

This device starts an auto precharge on the rising edge of the clock BL/2 or BL/2 - 2 +

RU(tRTP/tCK) clock cycles later than the READ with auto precharge command, which-

ever is greater. For auto precharge calculations, see the PRECHARGE and Auto Pre-

charge Clarification table.

216-Ball and 220-Ball, Dual-Channel LPDDR2 SDRAM

PRECHARGE Command

09005aef85eb530a

216b_220b_2ch_2e0e_embedded_lpddr2.pdf – Rev. F 08 /16 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

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