EDBA164B4PK-1DITF-R datasheet(31/152 Pages) MICRON

31 / 152 page

DQ, DM, DQS_t, and DQS_c voltage levels must be between VSSQ and VDDQ during the

power-off sequence to avoid latchup. CK_t, CK_c, CS_n, and CA input levels must be be-

tween VSS and VDD2 during the power-off sequence to avoid latchup.

Tx is the point where any power supply drops below the minimum value specified in

the Recommended DC Operating Conditions table.

Tz is the point where all power supplies are below 300mV. After Tz, the device is pow-

ered off.

Required Power Supply Conditions Between Tx and Tz:

•VDD1 must be greater than VDD2 - 200mV

•VDD1 must be greater than VDDQ - 200mV

•VREF must always be less than all other supply voltages

The voltage difference between VSS and VSSQ must not exceed 100mV.

For supply and reference voltage operating conditions, see Recommended DC Operat-

ing Conditions table.

Uncontrolled Power-Off Sequence

When an uncontrolled power-off occurs, the following conditions must be met:

• At Tx, when the power supply drops below the minimum values specified in the Rec-

ommended DC Operating Conditions table, all power supplies must be turned off and

all power-supply current capacity must be at zero, except for any static charge re-

maining in the system.

• After Tz, the point at which all power supplies first reach 300mV, the device must pow-

er off. The time between Tx and Tz must not exceed tPOFF. During this period, the rel-

ative voltage between power supplies is uncontrolled. VDD1 and VDD2 must decrease

with a slope lower than 0.5 V/μs between Tx and Tz.

An uncontrolled power-off sequence can occur a maximum of 400 times over the life of

the device.

Table 11: Power-Off Timing

Parameter

Symbol

Min

Max

Unit

Maximum power-off ramp time

tPOFF

–

sec

Mode Register Definition

The LPDDR2 device contains a set of mode registers used for programming device op-

erating parameters, reading device information and status, and for initiating special op-

erations such as DQ calibration, ZQ calibration, and device reset.

Mode Register Assignments and Definitions

The MRR command is used to read from a register. The MRW command is used to write

to a register. An “R” in the access column of the mode register assignment table indi-

cates read-only; a “W” indicates write-only; “R/W” indicates read or write capable or

enabled.

216-Ball and 220-Ball, Dual-Channel LPDDR2 SDRAM

Mode Register Definition

09005aef85eb530a

216b_220b_2ch_2e0e_embedded_lpddr2.pdf – Rev. F 08 /16 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

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