ADuCM4050

Data Sheet

Rev. A | Page 14 of 46

Parameter

Symbol

Min

Typ

Max

Unit

Test Conditions/Comments

ENABLE AND THREE-STATE SERIAL PORTS

Switching Characteristics

5

ns

160

ns

1

This specification is referenced to the sample edge.

2

This specification indicates the minimum instantaneous width or period that can be tolerated due to duty cycle variation or jitter on the external SPORT Clock.

3

These specifications are referenced to the drive edge.

DRIVE EDGE

SPT0_ACLK/SPT0_BCLK

(SPORT CLOCK)

SPT0_AFS/SPT0_BFS

(FRAME SYNC)

SPT0_AD0/SPT0_BD0

(DATA CHANNEL A/B)

SAMPLE EDGE

Figure 3. Serial Ports (Data Receive Mode through Internal Clock)

DRIVE EDGE

SPT0_A/SPT0_BCLK

(SPORT CLOCK)

SPT0_AFS/SPT0_BFS

(FRAME SYNC)

SPT0_AD0/SPT0_BD0

(DATA CHANNEL A/B)

SAMPLE EDGE

Figure 4. Serial Ports (Data Transmit Mode through Internal Clock)

DRIVE EDGE

SPT0_ACLK/SPT0_BCLK

(SPORT CLOCK)

SPT0_AFS/SPT0_BFS

(FRAME SYNC)

SPT0_AD0/SPT0_BD0

(DATA CHANNEL A/B)

SAMPLE EDGE

Figure 5. Serial Ports (Data Receive Mode through External Clock)