ADUCM4050BCPZ-R7 datasheet(29/46 Pages) AD

29 / 46 page

Data Sheet

ADuCM4050

Rev. A | Page 29 of 46

MEMORY ARCHITECTURE

The internal memory of the ADuCM4050 MCU is shown in

Figure 22. It incorporates 512 kB of embedded flash memory for

program code and nonvolatile data storage, 96 kB of data SRAM,

and 32 kB of SRAM (configured as instruction space or data space).

SRAM Region

This memory space contains the application instructions and

variables data, which must be accessed in real time. It supports

read/write access by the ARM Cortex-M4F core and read/write

DMA access by system peripherals. Byte, half-word and word

accesses are supported.

SRAM is divided into 96 kB data SRAM and 32 kB instruction

SRAM. If instruction SRAM is not enabled, then the associated

32 kB can be mapped as data SRAM, resulting in 128 kB of data

SRAM.

When the cache controller is enabled, 4 kB of the instruction

SRAM is reserved as cache memory. Optional parity bit error

detection is available on all SRAM memories. Multiple parity

bits are associated with each 32-bit word.

In hibernate mode, up to 124 kB of SRAM can be retained in

the following ways:

•

124 kB of data SRAM

•

96 kB of data SRAM and 28 kB of instruction SRAM

MMRs (Peripheral Control and Status)

For the address space containing MMRs, refer to Figure 22.

These registers provide control and status for on-chip

peripherals of the ADuCM4050 MCU.

For more information about the MMRs, refer to the

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with

Integrated Power Management Hardware Reference.

Flash Memory

The ADuCM4050 MCU includes 512 kB of embedded flash

memory, which is accessed using a flash controller. The flash

controller is coupled with a cache controller. A prefetch

mechanism is implemented in the flash controller to optimize

code performance.

Flash writes are supported by a keyhole mechanism via APB

writes to MMRs. The flash controller provides support for

DMA-based keyhole writes.

The device supports the following with consideration to flash

integrity:

•

A fixed user key required for running protected commands,

including mass erase and page erase.

•

An optional and user definable user failure analysis key

(FAA key).

•

An optional and user definable write protection for user-

accessible memory.

•

8-bit ECC.

Cache Controller

The ADuCM4050 MCU has an optional 4 kB instruction cache.

In certain applications, enabling the cache and executing the code

can result in lower power consumption rather than operating

directly from flash. When enabling the cache controller, 4 kB

of instruction SRAM is reserved as cache memory. In hibernate

mode, the cache memory is not retained.

0x0000_0000

0x0008 0000

512kB FLASH MEMORY

0x1000_0000

0x1000_8000

INSTRUCTION SRAM BANK 1,

INSTRUCTION SRAM BANK 2,

INSTRUCTION SRAM BANK 7

(32kB)

0x2000_0000

SYSTEM SRAM BANK 0 (16kB)

0x2000_4000

0x2004_0000

SYSTEM SRAM BANK 3 (16kB)

0x2004_4000

0x2004_8000

SYSTEM SRAM BANK 4 (16kB)

RESERVED

0x4000_0000

0x4000_002C

RESERVED

GENERAL-PURPOSE TIMER 0

0x4000_0400

0x4000_042C

GENERAL-PURPOSE TIMER 1

0x4000_0800

0x4000_082C

GENERAL-PURPOSE TIMER 2

0x4000_0C00

0x4000_0C3C

RGB TIMER

SYSTEM SRAM BANK 5 (32kB)

0x2005_0000

0x2005_4000

SYSTEM SRAM BANK 6 (16kB)

RESERVED

0x4000_1000

0x4000_10E8

REAL TIME CLOCK 0 (RTC0)

RESERVED

0x4000_1400

0x4000_14E8

REAL TIME CLOCK 1 (RTC1)

0x4000_2000

0x4000_2040

SYSTEM ID AND DEBUG ENABLE

0x4000_2C00

0x4000_2C1C

WATCHDOG TIMER

0x4000_3000

0x4000_305C

I2C 0 MASTER/SLAVE

0x4000_4000

0x4000_4038

SPI 0 MASTER/SLAVE

0x4000_4400

0x4000_4438

SPI 1 MASTER/SLAVE

0x4000_5000

0x4000_504C

UART 0

RESERVED

0x4001_8000

0x4001_8064

FLASH CONTROLLER

0x4002_0000

0x4002_00F8

GPIO

RESERVED

0x4002_4000

0x4002_4038

SPIH 0 MASTER/SLAVE

0x4003_8000

0x4003_806C

SPORT 0

0x4004_0000

0x4004_0018

PROGRAMMABLE CRC ENGINE

0x4004_0400

0x4004_0418

RANDOM NUMBER GENERATOR

0x4004_4000

0x4004_40C8

CRYPTOGRAPHIC ACCELERATOR

0x4004_C000

0x4004_C814

POWER MANAGEMENT, EXTERNAL

INTERRUPTS, CLOCKING,

MISCELLANEOUS REGISTERS

RESERVED

0x4000_5C00

0x4000_5C0F

BEEPER 0

RESERVED

0x4000_5400

0x4000_544C

UART 1

0x4001_0000

0x4001_0FE4

DMA 0

RESERVED

0x4000_7000

0x4000_70C4

ADC0

Figure 22. ADuCM4050 Memory Map—SRAM Mode 0

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