ADUCM4050BCPZ-R7 datasheet(30/46 Pages) AD

30 / 46 page

ADuCM4050

Data Sheet

Rev. A | Page 30 of 46

SYSTEM INTEGRATION FEATURES

The ADuCM4050 MCU provides several features for

development of ultra low power, secure, and robust systems.

Reset

There are four kinds of resets: external, power-on, watchdog

timeout, and software system reset. The software system reset is

provided as part of the ARM Cortex-M4F core. The

SYS_HWRST pin is toggled to perform a hardware reset.

Booting

The ADuCM4050 MCU supports two boot modes: booting from

internal flash and upgrading software through UART download

(see Table 24). If SYS_BMODE0 (Pin P1_01) is pulled low

during power-up or a hard reset, the MCU enters into serial

download mode. In this mode, an on-chip loader routine

initiates in the kernel, which configures the UART port and

communicates with the host to manage the firmware upgrade

via a specific serial download protocol.

Table 24. Boot Modes

Boot Mode

Description

UART download mode.

Flash boot. Boot from integrated flash memory.

Power Management and Modes

The ADuCM4050 MCU has an integrated power management

system that optimizes performance and extends the battery life

of the device. The power management system consists of the

following:

•

Integrated 1.2 V low dropout regulator (LDO) and optional

capacitive buck regulator

•

Integrated power switches for low standby current in

hibernate and shutdown modes

Additional power management features include the following:

•

Customized clock gating for active modes

•

Power gating to reduce leakage in hibernate and shutdown

modes

•

Flexible sleep modes

•

Shutdown mode with no retention

•

Optional high efficiency buck converter to reduce power

•

Integrated low power oscillators

The PMU provides control of the ADuCM4050 MCU power

modes and allows the ARM Cortex-M4F to control the clocks

and power gating to reduce the power consumption. Several

power modes are available, offering options to balance power

consumption and functionality. The power modes available in the

ADuCM4050 are described in the following sections.

Active Mode

In active mode, all peripherals can be enabled. Active power is

managed by optimized clock management. See Table 3 for

details on active mode current consumption.

Flexi Mode

In flexi mode, the ARM Cortex-M4F core is clock gated, but the

remainder of the system is active. No instructions can be executed

in this mode, but DMA transfers can continue between peripherals

as well as memory to memory. See Table 4 for details on flexi mode

current consumption.

Hibernate Mode

Hibernate mode provides state retention, configurable SRAM

and port pin retention, a limited number of wake-up interrupts

(SYS_WAKEx, UART0_RX, and optionally, RTC0 and RTC1

(FLEX_RTC™)).

Shutdown Mode

Shutdown mode is the deepest sleep mode, in which all the digital

and analog circuits are powered down with an option to wake

from four possible wake-up sources. The RTC0 can be (optionally)

enabled in this mode, and the device can be periodically woken

up by the RTC0 interrupt.

Shutdown Mode—Fast Wake-Up

This mode has a faster wake-up time than shutdown mode at

the expense of higher power consumption. See Table 25 for

wake-up time specifications.

Power Management and Control

The following features are available for power management and

control:

•

Voltage range of 1.74 V to 3.6 V using a single supply (such

as the CR2032 coin cell battery).

•

GPIOs are driven directly from the battery. The pin state is

retained in hibernate and shutdown modes. The GPIO

configuration is only retained in hibernate mode.

•

Wake-up from external interrupts (via GPIOs),

UART0_RX interrupt, and RTCs for hibernate mode.

•

Wake-up from external interrupts (via GPIOs) and RTC0

for shutdown mode.

•

Optional high power buck converter for 1.2 V full on support

(MCU use only). See Figure 23 for suggested external circuitry.

BUCK

ENABLED

LDO

NOTES

1. FOR DESIGNS IN WHICH THE OPTIONAL BUCK IS NOT USED,

THE FOLLOWING PINS MUST BE LEFT UNCONNECTED: VDCDC_CAP1P,

VDCDC_CAP1N, VDCDC_OUT, VDCDC_CAP2P, AND VDCDC_CAP2N.

VDCDC_CAP1 P

VBAT

0.1µF

1µF

0.1µF

VDCDC_CAP1N

VDCDC_OUT

VDCDC_CAP2 P

0.47µF

VLDO_OUT

VDCDC_CAP2N

Figure 23. Buck Enable Design

ADUCM4050BCPZ-R7 датащи(PDF) 30 Page - Analog Devices

ADUCM4050BCPZ-R7 датащи(HTML) 30 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46

датащи скачать

ссылки URL