ADUCM4050BCPZ-R7 datasheet(31/46 Pages) AD

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Data Sheet

ADuCM4050

Rev. A | Page 31 of 46

Table 25. Power Modes Wake-Up Times

Mode

VTOR1

Root Clock

HCLK/PCLK

Wake-Up Time

Flexi

Flash

HFOSC

26 MHz

1.605 µs

Hibernate

Flash

HFOSC

26 MHz

10.356 µs

SRAM

HFOSC

26 MHz

4.984 µs

Flash

HFXTAL

26 MHz

686.452 µs

Flash

PLL_HFOSC

26 MHz

14.487 µs

Flash

PLL_HFXTAL

26 MHz

742.668 µs

Flash

PLL_HFOSC

52 MHz

15.730 µs

Flash

PLL_HFXTAL

52 MHz

726.101 µs

Shutdown

Flash

HFOSC

26 MHz

68.144 ms

Shutdown (Fast Wake-Up)

Flash

HFOSC

26 MHz

1.220 ms

VTOR means vector table offset register.

Security Features

The ADuCM4050 MCU provides a combination of hardware

and software protection mechanisms that lock out access to the

device in secure mode, but grant access in open mode. These

mechanisms include the password protected slave boot mode

(UART), as well as password protected serial wire debug (SWD)

interfaces. Mechanisms are provided to protect the device

contents (flash, SRAM, CPU registers, and peripheral registers)

from being read through an external interface by an

unauthorized user. This is referred to as read protection.

It is possible to protect the device from being reprogrammed in

circuit with unauthorized code. This is referred to as in circuit

write protection.

The device can be configured with no protection, read protection,

or read and in circuit write protection. It is not necessary to

provide in circuit write protection without read protection.

This product includes security features that can be used to protect

embedded nonvolatile memory contents and prevent execution

of unauthorized code. When security is enabled on this device

(either by the ordering party or the subsequent receiving parties),

the ability of Analog Devices to conduct failure analysis on

returned devices is limited. Contact Analog Devices for details

on the failure analysis limitations for this device.

Cryptographic Accelerator

The cryptographic accelerator is a 32-bit APB DMA capable

peripheral. There are two 128-bit buffers provided for data

input/output operations. These buffers read in or read out

128 bits in four data accesses. Big endian and little endian data

formats are supported, as are the following modes:

•

ECB mode—AES mode

•

CTR mode

•

CBC mode

•

Message authentication code (MAC) mode

•

CCM/CCM* mode

•

SHA-256 modes

•

Protected key storage with key wrap and unwrap—HMAC

signature generation

True Random Number Generator (TRNG)

The TRNG is used during operations where nondeterministic

values are required. This can include generating challenges for

secure communication or keys used for an encrypted commu-

nication channel. The generator can run multiple times to

generate a sufficient number of bits for the strength of the

intended operation. The true random number generator can

seed a deterministic random bit generator.

Reliability and Robustness Features

The ADuCM4050 MCU provides several features that can

enhance or help achieve certain levels of system safety and

reliability. Whereas the level of safety is mainly dominated by

system considerations, the following features are provided to

enhance robustness.

ECC Enabled Flash Memory

The entire flash array is protected to either correct single-bit

errors or detect two bit errors per 64-bit flash data.

Multiparity Bit Protected SRAM

Each word of the SRAM and cache memory is protected by

multiple parity bits to allow detection of random soft errors.

Software Watchdog

The on-chip watchdog timer can provide software-based

supervision of the ADuCM4050 core.

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