ADUCM4050BCPZ-R7 datasheet(28/46 Pages) AD

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ADuCM4050

Data Sheet

Rev. A | Page 28 of 46

THEORY OF OPERATION

ARM CORTEX-M4F PROCESSOR

The ARM Cortex-M4F core is a 32-bit reduced instruction set

computer (RISC). The length of the data can be 8 bits, 16 bits,

or 32 bits. The length of the instruction word is 16 bits or

32 bits. The processor has the following features:

•

ARM Cortex-M4F architecture

•

Thumb-2 instruction set architecture (ISA) technology

•

Three-stage pipeline with branch speculation

•

Low latency interrupt processing with tail chaining

•

Single-cycle multiply

•

Hardware divide instructions

•

Nested vectored interrupt controller (NVIC) (72 interrupts

and 8 priorities)

•

Six hardware breakpoints and one watchpoint (unlimited

software breakpoints using the Segger JLink debug probe)

•

Bit banding support

•

Trace support—instruction trace macrocell (ITM), trace

port interface unit (TPIU), and data watchpoint and trace

(DWT) triggers and counters

•

Memory protection unit (MPU)

•

Eight-region MPU with subregions and background region

•

Programmable clock generator unit

•

Configurable for ultralow power operation

•

Deep sleep modes, dynamic power management

•

Programmable clock generator unit

•

Floating point unit (FPU)

•

Supports single-precision add, subtract, multiply, divide,

multiply and accumulate, and square root operations

•

Provides conversions between fixed point and floating

point data formats, and floating point constant instructions

ARM Cortex-M4F Subsystem

The ADuCM4050 MCU memory map (see the ADuCM4050

Ultra Low Power ARM Cortex-M4F MCU with Integrated

Power Management Hardware Reference) is based on the ARM

Cortex-M4F memory model. By retaining the standardized

memory mapping, it is easier to port applications across ARM

Cortex-M4F platforms. The ADuCM4050 application

development is based on memory blocks across code and

SRAM regions. Sufficient internal memory is available via

internal SRAM and internal flash.

Code Region

Accesses in the code region (0x0000_0000 to 0x0007_FFFF

except 0x0007_F000 to 0x0007_FFFF, which is meant for

protected key storage) are performed by the core and target the

memory and cache resources.

SRAM Region

Accesses in the SRAM region (see Figure 22) are performed by

the ARM Cortex-M4F core. The SRAM region of the core can

act as a data region for an application.

•

Internal SRAM data region. This space can contain

read/write data. Internal SRAM can be partitioned between

code and data (the SRAM region in the ARM Cortex-M4F

space) in 32 kB blocks. Access to this region occurs at core

clock speed with no wait states. The SRAM data region also

supports read/write access by the ARM Cortex-M4F core

and read/write DMA access by system devices.

•

System memory mapped registers (MMRs). Various system

MMRs reside in this region.

System Region

Accesses in this region (0xE000_0000 to 0xFFFF_FFFF) are

performed by the ARM Cortex-M4F core and handled within

the ARM Cortex-M4F platform. This system region includes

the following components:

•

CoreSight™ read only memory (ROM). The ROM table

entries (see the ARM Cortex-M4F Technical Reference

Manual) show the debug components of the processor.

•

ARM advanced peripheral bus (APB) peripheral. This

space is defined by ARM and occupies the bottom 256 kB

of the system region (0xE000_0000 to 0xE004_0000). The

space supports read/write access by the ARM Cortex-M4F

core to the internal peripherals of the ARM core (NVIC,

system control space (SCS), and wake-up interrupt controller

(WIC)) and CoreSight ROM. It is not accessible by system

DMA.

•

Platform control register. This space has registers within

the ARM Cortex-M4F platform component that control

the ARM core, its memory, and the code cache. It is

accessible by the ARM Cortex-M4F core (but not

accessible by system DMA).

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