Data Sheet

ADuCM4050

Rev. A | Page 43 of 46

SILICON ANOMALY

This anomaly list describes the known bugs, anomalies, and workarounds for the ADuCM4050. These anomalies represent the currently

known differences between revisions of the ADuCM4050 product and the functionality specified in the ADuCM4050 data sheet and the

hardware reference manual.

Analog Devices, Inc., is committed, through future silicon revisions, to continuously improve silicon functionality. Analog Devices tries

to ensure that these future silicon revisions remain compatible with your present software/systems by implementing the recommended

workarounds outlined here.

ADuCM4050 FUNCTIONALITY ISSUES

Silicon Revision Identifier

Silicon Status

No. of Reported Anomalies

0.1

Released

3 (21000011, 21000016, 21000017)

A silicon revision number with the form x.y is branded on all devices. The silicon revision can be electronically determined by reading Bits[3:0]

of the SYS_CHIPID register. SYS_CHIPID = 0x1 indicates Silicon Revision 0.1, and SYS_CHIPID = 0x0 indicates Silicon Revision 0.0.

FUNCTIONALITY ISSUES

Issue

Workaround

Revision

0.1

Issue

enabled, the transaction is paused by holding the SCL (Pin P0_04) line low. This function works as expected when the

next read happens after the clock is stretched (that is, after the overflow is detected). However, if the read occurs after

is lost.

Workaround

register to ensure that that Rx FIFO is never read at the same time that the overflow is asserted.

Revision

0.1

Table 35. 21000017—SPI Read Command Mode Does Not Work Properly when SPI_CNT is 1 and DMA is Enabled

Issue

When SPI master is enabled and uses the DMA mode with SPI_CNT = 1, the read command mode may not function

properly. Consider the following configurations: SPI_RD_CTL = 0x07; SPI_CNT = 1; the transmit and receive DMA

channels are configured for 1 half-word.

In this configuration, the read command sent in the first byte on the MOSI output is repeated in the second byte (in the

address slot). Therefore, the slave device responds on the MISO line with whatever content is at the address equivalent to the

read command value (for example, if the read command is 0xB, the response is the data read from Slave Address 0xB).

Workaround

The following workarounds can be used. Utilize the overlap mode to align the transmit/receive SPI operations and

discard the junk bytes, as follows:

1. Set SPI_RD_CTL.OVERLAP = 1 to enable overlap mode.

2. Set SPI_RD_CTL.TXBYTES = 1 to configure a single transmit byte (8-bit address register).

3. Set SPI_CNT.VALUE = 3 to configure the transfer count: one byte for the address register, one byte for the command,

and one dummy byte to obtain the read value.

4. On the receive side, discard the first two junk bytes received during the transfer of the address and command bytes

before processing the actual read value in the third byte.

Alternatively, do not use Tx DMA operation on the SPI transmit side, by taking the following steps:

1. Enable only SPI RX DMA requests.

2. Fill the SPI Tx FIFO by using core accesses to write the SPI_TX register.

3. Perform a dummy read of the SPI_RX register to kick off the SPI transfers.

Revision

0.1