ADUCM4050BCPZ-R7 datasheet(5/46 Pages) AD

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Data Sheet

ADuCM4050

Rev. A | Page 5 of 46

POWER SUPPLY CURRENT SPECIFICATIONS

Active Mode

Table 3.

Parameter

Min Typ1 Max2 Unit

Test Conditions/Comments

ACTIVE MODE3

Current consumption when VBAT = 3.0 V

Buck Enabled

1.27

2.71

Code executing from flash, cache enabled, system peripheral clock (PCLK) disabled,

advanced high performance clock (HCLK) = 26 MHz4

1.83

3.28

Code executing from flash, cache disabled, PCLK disabled, HCLK = 26 MHz4

1.40

2.84

Code executing from flash, cache enabled, PCLK = 26 MHz, HCLK = 26 MHz4

1.97

3.41

Code executing from flash, cache disabled, PCLK = 26 MHz, HCLK = 26 MHz4

2.33

3.78

Code executing from flash, cache enabled, PCLK disabled, HCLK = 52 MHz5

2.94

4.39

Code executing from flash, cache disabled, PCLK disabled, HCLK = 52 MHz5

2.59

4.04

Code executing from flash, cache enabled, PCLK = 52 MHz, HCLK = 52 MHz5

3.21

4.65

Code executing from flash, cache disabled, PCLK = 52 MHz, HCLK = 52 MHz5

1.43

2.87

Code executing from SRAM, PCLK disabled, HCLK = 26 MHz4

1.56

3.00

Code executing from SRAM, PCLK = 26 MHz, HCLK = 26 MHz4

2.64

4.09

Code executing from SRAM, PCLK disabled, HCLK = 52 MHz5

2.90

4.35

Code executing from SRAM, PCLK = 52 MHz, HCLK = 52 MHz5

Dynamic Current

µA/MHz Code executing from flash, cache enabled

Buck Disabled

2.34

4.78

Code executing from flash, cache enabled, PCLK disabled, HCLK = 26 MHz4

3.38

5.82

Code executing from flash, cache disabled, PCLK disabled, HCLK = 26 MHz4

2.60

5.04

Code executing from flash, cache enabled, PCLK = 26 MHz, HCLK = 26 MHz4

3.65

6.09

Code executing from flash, cache disabled, PCLK = 26 MHz, HCLK = 26 MHz4

4.46

6.90

Code executing from flash, cache enabled, PCLK disabled, HCLK = 52 MHz5

5.61

8.05

Code executing from flash, cache disabled, PCLK disabled, HCLK = 52 MHz5

4.98

7.42

Code executing from flash, cache enabled, PCLK = 52 MHz, HCLK = 52 MHz5

6.14

8.58

Code executing from flash, cache disabled, PCLK = 52 MHz, HCLK = 52 MHz5

2.66

5.10

Code executing from SRAM, PCLK disabled, HCLK = 26 MHz4

2.92

5.36

Code executing from SRAM, PCLK = 26 MHz, HCLK = 26 MHz4

5.08

7.52

Code executing from SRAM, PCLK disabled, HCLK = 52 MHz5

5.60

8.04

Code executing from SRAM, PCLK = 52 MHz, HCLK = 52 MHz5

Dynamic Current

µA/MHz Code executing from flash, cache enabled

TJ = 25°C

TJ = 85°C

The code being executed is a prime number generation in a continuous loop, with high frequency RC oscillator (HFOSC) as the system clock source.

Zero wait states and low buck load.

One wait state and high buck load.

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