ADN8835ACPZ-R7 datasheet(23/27 Pages) AD

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Data Sheet

ADN8835

Rev. B | Page 23 of 27

PCB LAYOUT GUIDELINES

Figure 40. System Block Diagram

BLOCK DIAGRAMS AND SIGNAL FLOW

The ADN8835 integrates analog signal conditioning blocks, a

load protection block, and a TEC controller power stage, all in a

single IC. To achieve the best possible circuit performance,

attention must be paid to keep the noise of the power stage from

contaminating the sensitive analog conditioning and protection

circuits. In addition, the layout of the power stage must be

performed such that the IR losses are minimized to obtain the

best possible electrical efficiency.

The system block diagram of the ADN8835 is shown in Figure 40.

GUIDELINES FOR REDUCING NOISE AND

MINIMIZING POWER LOSS

Each PCB layout is unique because of the physical constraints

defined by the mechanical aspects of a given design. In addition,

several other circuits work in conjunction with the TEC

controller; these circuits have their own layout requirements.

Therefore, there are always compromises that must be made for a

given system. However, to minimize noise and keep power losses

to a minimum during the PCB layout process, observe the

following guidelines.

General PCB Layout Guidelines

Switching noise can interfere with other signals in the system;

therefore, the switching signal traces must be placed away from

the power stage to minimize the effect. If possible, place the

ground plate between the small signal layer and power stage

layer as a shield.

Supply voltage drop on traces is also an important consideration

because it determines the voltage headroom of the TEC controller

at high currents. For example, if the supply voltage from the front-

end system is 3.3 V, and the voltage drop on the traces is 0.5 V,

PVIN sees only 2.8 V, which limits the maximum voltage of the

linear regulator as well as the maximum voltage across the TEC. To

mitigate the voltage waste on traces and impedance interconnec-

tion, place the ADN8835 and the input decoupling components

close to the supply voltage terminal. This placement not only

improves the system efficiency but also provides better regulation

performance at the output.

To prevent the noise signal from circulating through the ground

plates, reference all of the sensitive analog signals to AGND and

connect AGND to PGNDS using only a single-point connection.

This connection ensures that the switching currents of the power

stage do not flow into the sensitive AGND node.

PWM Power Stage Layout Guidelines

The PWM power stage consists of a MOSFET pair that forms a

switch mode output that switches current from PVINS to the

load via an LC filter. The ripple voltage on the PVINS pin is

caused by the discontinuous current switched by the PWM side

MOSFETs. This rapid switching causes voltage ripple to form at

the PVINS input, which must be filtered using a bypass capaci-

tor. Place a 10 µF capacitor as close as possible to the PVINS pin

to connect PVINS to PGNDS. Because the 10 µF capacitor is

sometimes bulky and has higher ESR and ESL, a 100 nF decou-

pling capacitor is usually used in parallel with it, placed between

PVINS and PGNDS.

Because the decoupling is part of the pulsating current loop,

which carries high di/dt signals, the traces must be short and

wide to minimize the parasitic inductance. As a result, this

capacitor is usually placed on the same side of the board as the

ADN8835 to ensure short connections. If the layout requires

that a 10 µF capacitor be on the opposite side of the PCB, use

multiple vias to reduce via impedance.

The layout around the SW node is also critical because it switches

between PVINS and ground rapidly, which makes this node a

strong EMI source. Keep the copper area that connects the SW

node to the inductor small to minimize parasitic capacitance

between the SW node and other signal traces. The small copper

area helps minimize noise on the SW node due to excessive

charge injection. However, in high current applications, the

copper area can be increased reasonably to provide a heat sink

and to sustain high current flow.

TEMPERATURE

SIGNAL

CONDITIONING

TEC

VOLTAGE

LIMITING

TEC

CURRENT

LIMITING

TEC

VOLTAGE

SENSING

TEC

CURRENT

SENSING

TEC

DRIVER

OBJECT

THERMOELECTRIC

COOLER

(TEC)

TEMPERATURE

ERROR

COMPENSATION

TEMPERATURE

SENSOR

SOURCE OF

ELECTRICAL

POWER

TARGET

TEMPERATURE

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