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ADN8835

Data Sheet

Rev. B | Page 14 of 27

ANALOG PID CONTROL

The ADN8835 integrates two self correcting, auto-zeroing

amplifiers (Chopper 1 and Chopper 2). The Chopper 1 amplifier

takes a thermal sensor input and converts or regulates the input

to a linear voltage output. The OUT1 voltage is proportional to the

object temperature. The OUT1 voltage is fed into the compensa-

tion amplifier (Chopper 2) and is compared with a temperature

setpoint voltage, which creates an error voltage that is propor-

tional to the difference. For autonomous analog temperature

control, Chopper 2 can implement a PID network as shown in

Figure 26 to set the overall stability and response of the thermal

loop. Adjusting the PID network optimizes the step response of

the TEC control loop. A compromised settling time and the

maximum current ringing become available when this

adjustment is done. To adjust the compensation network, see

the PID Compensation Amplifier (Chopper 2) section.

DIGITAL PID CONTROL

The ADN8835 can also be configured for use in a software

controlled PID loop. In this scenario, the Chopper 1 amplifier

can either be left unused or configured as a thermistor input

amplifier connected to an external temperature measurement

analog-to-digital converter (ADC). For more information, see

the Thermistor Amplifier (Chopper 1) section. If Chopper 1 is

left unused, tie IN1N and IN1P to AGND.

The Chopper 2 amplifier is used as a buffer for the external

DAC, which controls the temperature setpoint. Connect the

DAC to IN2P and short the IN2N and OUT2 pins together. See

Figure 27 for an overview of how to configure the ADN8835

external circuitry for digital PID control.

POWERING THE CONTROLLER

The ADN8835 operates at an input voltage range of 2.7 V to

5.5 V that is applied to the PVINS pins and PVINL pins. The

VDD pin is the input power for the driver and internal reference.

The PVINS and the PVINL input power pins are for the PWM

driver and the linear driver, respectively. Apply the same input

voltage to all power input pins. In some circumstances, an RC

low-pass filter can be added between the PVINS/PVINL and

the VDD pins to prevent high frequency noise from entering

VDD, as shown in Figure 27. The capacitor and resistor values

are typically 10 Ω and 0.1 µF, respectively.

When configuring the power supply to the ADN8835, keep in

mind that at high current loads, the input voltage may drop

substantially due to a voltage drop on the wires between the

front-end power supply and the PVINS and the PVINL pins.

Leave a proper voltage margin when designing the front-end

power supply to maintain the performance. Minimize the trace

length from the power supply to the PVINS and the PVINL

pins to help mitigate the voltage drop.

Figure 27. TEC Controller in a Digital Temperature Control Loop

ADN8835

L = 1µH

VIN

2.7V TO 5.5V

TEC

SFB

LDR

PGNDS

PVINL

PVINS

VDD

ILIM

VLIM/SD

ITEC

IN2P

VTEC

TEC

VOLTAGE

LIMIT

2.5V VREF

–

EN/SY

CSW_OUT

10µF

FSW = 2MHz

CL_OUT

0.1µF

CIN

10µF

CVDD

0.1µF

PGNDL

ENABLE

IN1N

IN1P

VREF

AGND

IN2N OUT2

OUT1

RV1

RV2

RC1

RC2

COOLING AND HEATING

TEC CURRENT LIMITS

CVREF

0.1uF

2.5V VREF

TEC VOLTAGE READBACK

TEC CURRENT READBACK

TEMPERATURE SET

RFB

RBP

NTC

THERMISTOR

RTH

TEMPERATURE

READBACK

ADC

DAC

2.5V VREF

TMPGD

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