ADN8835ACPZ-R7 datasheet(15/27 Pages) AD

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Data Sheet

ADN8835

Rev. B | Page 15 of 27

ENABLE AND SHUTDOWN

To enable the ADN8835, apply a logic high voltage to the

EN/SY pin while the voltage at the VLIM/SD pin is above the

maximum shutdown threshold of 0.07 V. If either the EN/SY pin

voltage is set to logic low or the VLIM/SD voltage is below 0.07 V,

the controller goes into an ultralow current state. The current

drawn in shutdown mode is 350 µA typically. Most of the current

is consumed by the VREF circuit block, which is always on even

when the device is disabled or shut down. The device can also

be enabled when an external synchronization clock signal is

applied to the EN/SY pin, and the voltage at VLIM/SD input is

above 0.07 V. Table 6 shows the combinations of the two input

signals that are required to enable the ADN8835.

Table 6. Enable Pin Combinations

EN/SY Input

VLIM/SD Input

Controller

>2.1 V

>0.07 V

Enabled

Switching Between High

(>2.1 V) and Low (<0.8 V)

>0.07 V

Enabled

<0.8 V

No effect1

Shutdown

Floating

No effect1

Shutdown

No effect1

≤0.07 V

Shutdown

No effect means this signal has no effect in shutting down or in enabling the

device.

OSCILLATOR CLOCK FREQUENCY

The ADN8835 has an internal oscillator that generates a 2.0 MHz

switching frequency for the PWM output stage. This oscillator is

active when the enabled voltage at the EN/SY pin is set to a logic

level higher than 2.1 V and the VLIM/SD pin voltage is greater

than the shutdown threshold of 0.07 V.

External Clock Operation

The PWM switching frequency of the ADN8835 can be synchro-

nized to an external clock from 1.85 MHz to 3.25 MHz, applied

to the EN/SY input pin, as shown on Figure 28.

Figure 28. Synchronize to an External Clock

Connecting Multiple ADN8835 Devices

Multiple ADN8835 devices can be driven from a single master

clock signal by connecting the external clock source to the

EN/SY pin of each slave device. The input ripple can be greatly

reduced by operating the ADN8835 devices 180° out of phase from

each other and placing an inverter at one of the EN/SY pins, as

shown in Figure 29.

Figure 29. Multiple ADN8835 Devices Driven from a Master Clock

TEMPERATURE LOCK INDICATOR

The TMPGD pin outputs logic high when the temperature

error amplifier output voltage, VOUT1, reaches the IN2P

temperature setpoint (TEMPSET) voltage. The TMPGD pin has a

detection range between 1.46 V and 1.54 V of VOUT1 and hysteresis.

The TMPGD function allows direct interfacing either to the

microcontrollers or to the supervisory circuitry.

SOFT START ON POWER-UP

The ADN8835 has an internal soft start circuit that generates a

ramp with a typical 150 ms profile to minimize inrush current

during power-up. The settling time and the final voltage across

the TEC depends on the TEC voltage required by the control

voltage of voltage loop. The higher the TEC voltage is, the longer it

requires to increase.

When the ADN8835 is first powered up, the linear side discharges

the output of any prebias voltage. As soon as the prebias is elimi-

nated, the soft start cycle begins. During the soft start cycle, both

the PWM and linear outputs track the internal soft start ramp

until they reach midscale, where the control voltage, VC, is equal

to the bias voltage, VB. From the midscale voltage, the PWM and

linear outputs are then controlled by VC and diverge from each

other until the required differential voltage is developed across

the TEC or the differential voltage reaches the voltage limit. The

voltage developed across the TEC depends on the control point

at that moment in time. Figure 30 shows an example of the soft

start profile in cooling mode. Note that, as both the LDR and SFB

voltages increase with the soft start ramp and approach VB, the

ramp slows to avoid possible current overshoot at the point

where the TEC voltage starts to increase.

EXTERNAL CLOCK

SOURCE

ADN8835

AGND

EN/SY

ADN8835

EXTERNAL CLOCK

SOURCE

AGND

EN/SY

AGND

EN/SY

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