ADN8835ACPZ-R7 datasheet(22/27 Pages) AD

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ADN8835

Data Sheet

Rev. B | Page 22 of 27

conduction losses (PCOND), switching losses (PSW), and transition

losses (PTRAN). Other sources of power dissipation are usually

less significant at the high output currents of the application

thermal limit and can be neglected in approximation.

Use the following equation to estimate the power dissipation of

the buck regulator:

PLOSS = PCOND + PSW + PTRAN

Conduction Loss (PCOND)

The conduction loss consists of two parts: inductor conduction

loss (PCOND_L) and power switch conduction loss (PCOND_S).

PCOND = PCOND_L + PCOND_S

Inductor conduction loss is proportional to the DCR of the output

inductor, L. Using an inductor with low DCR enhances the overall

efficiency performance. Estimate inductor conduction loss by

PCOND_L = DCR × IOUT2

Power switch conduction losses are caused by the flow of the

output current through both the high-side and low-side power

switches, each of which has its own internal on resistance (RDSON).

Use the following equation to estimate the amount of power

switch conduction loss:

PCOND_S = (RDSON_HS × D + RDSON_LS × (1 − D)) × IOUT2

where:

RDSON_HS is the on resistance of the high-side MOSFET.

D is the duty cycle (D = VOUT/VIN).

RDSON_LS is the on resistance of the low-side MOSFET.

Switching Losses (PSW)

Switching losses are associated with the current drawn by the

controller to turn the power devices on and off at the switching

frequency. Each time a power device gate is turned on or off,

the controller transfers a charge from the input supply to the

gate, and then from the gate to ground. Use the following

equation to estimate the switching loss:

PSW = (CGATE_HS + CGATE_LS) × VIN2 × fSW

where:

CGATE_HS is the gate capacitance of the high-side MOSFET.

CGATE_LS is the gate capacitance of the low-side MOSFET.

fSW is the switching frequency.

For the ADN8835, the total of CGATE_HS + CGATE_LS is

approximately 1 nF.

Transition Losses (PTRAN)

Transition losses occur because the high-side MOSFET cannot

turn on or off instantaneously. During a switch node transition,

the MOSFET provides all the inductor current. The source to

drain voltage of the MOSFET is half the input voltage, resulting

in power loss. Transition losses increase with both load and input

voltage and occur twice for each switching cycle.

Use the following equation to estimate the transition loss:

PTRAN = 0.5 × VPVIN × IOUT × (tR + tF) × fSW

where:

VPVIN is the voltage at PVIN.

IOUT is the output current of the PWM regulator.

tR is the rise time of the switch node.

tF is the fall time of the switch node.

Linear Regulator Power Dissipation

In the ADN8835, the output voltage of linear regulator is

typically tied either to ground or VIN. The main power

dissipation in this case comes from the conduction loss of the

FETs and thus is quite low. When the load is light and the linear

regulator must operate in a linear region, the power dissipation

can be calculated using the following equation:

PLINEAR = ((VIN − VOUT) × IOUT) + (VIN × IGND)

where:

VIN and VOUT are the input and output voltages of the linear

regulator.

IOUT is the load current of the linear regulator.

IGND is the ground current of the linear regulator.

Power dissipation due to the ground current is generally small

and can be ignored for the purposes of this calculation.

THERMAL CONSIDERATION

To ensure that the ADN8835 operates below the maximum

junction temperature even at high load, careful attention must

be paid to provide a lower θJA value of the device. Typical

techniques for enhancing heat dissipation include using larger

copper layer and vias on the printed circuit board (PCB) and

adding a heat sink.

The ADN8835 LFCSP package has a large exposed pad (EPAD)

at the bottom that must be soldered to the analog ground plane

on the board. The majority of the heat of the device dissipates

through the EPAD. Therefore, the copper layer connected to the

EPAD as well as the vias on it must be optimized to conduct the

heat effectively. It is recommended to use at least a 6 × 6 via

array and distribute them evenly on the EPAD. Generally, it is

more effective to increase the number of vias than to increase

the diameter of the via within a limited area.

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