TMS320AV7110 datasheet(2/131 Pages) TI

2 / 131 page

DSP

TMS320AV7110

Revision 3.1

10/08/99 22:18

Page 2

Table of Contents

INTRODUCTION................................................................................................................................. 7

1.1

FEATURES ........................................................................................................................................ 7

PIN FUNCTIONS ................................................................................................................................. 8

2.1

PIN TYPES...................................................................................................................................... 11

ARCHITECTURE .............................................................................................................................. 12

3.1

FUNCTIONAL BLOCK DIAGRAM...................................................................................................... 12

3.2

OVERVIEW ..................................................................................................................................... 12

3.2.1

Transport bit-stream processing ........................................................................................... 14

3.2.2

Audio and Video data processing ......................................................................................... 14

3.3

SOFTWARE SYSTEM OVERVIEW ..................................................................................................... 14

ARM CPU............................................................................................................................................ 16

4.1

FEATURES ...................................................................................................................................... 16

4.2

BLOCK DIAGRAM........................................................................................................................... 16

4.3

RESOURCE MANAGEMENT.............................................................................................................. 17

TRAFFIC CONTROLLER (TC) ...................................................................................................... 18

5.1

FEATURES ...................................................................................................................................... 18

5.2

SDRAM INTERFACE...................................................................................................................... 19

5.3

PRIORITIZED INTERRUPTS .............................................................................................................. 23

5.4

MANAGING DMA TRANSFER ......................................................................................................... 23

5.5

VIDEO/AUDIO BUFFER MONITORING SUPPORT............................................................................... 23

5.6

TRANSFER OF VIDEO/AUDIO DATA FROM THE HIGH SPEED DATA INTERFACE (HSDI) TO

SDRAM .................................................................................................................................................... 24

MPEG TRANSPORT DECODER (TPP) ......................................................................................... 25

6.1

THE TPP MODULE ......................................................................................................................... 25

6.1.1

Features ................................................................................................................................ 25

6.1.2

Description............................................................................................................................ 25

6.1.3

Conditional access and Descrambling processing ............................................................... 26

6.1.4

Transport Parser Input Interface .......................................................................................... 26

6.2

HARDWARE SECTION FILTERING.................................................................................................... 27

6.2.1

Memory Map ......................................................................................................................... 28

6.2.2

Filter hardware definition..................................................................................................... 28

6.2.3

Filter Match Data Register definition ................................................................................... 29

6.2.4

Match Result Register Definition .......................................................................................... 30

6.2.5

Status Register Word Definition............................................................................................30

6.2.6

Filter Reset Control Register ................................................................................................ 31

6.2.7

Typical software process flow ............................................................................................... 31

6.2.8

CPU load assessment............................................................................................................ 32

6.3

HARDWARE CRC CIRCUIT ............................................................................................................. 33

VIDEO DECODER............................................................................................................................. 34

7.1

FEATURES ...................................................................................................................................... 34

7.2

DESCRIPTION ................................................................................................................................. 34

7.3

TRICK MODE.................................................................................................................................. 35

7.4

HIGH-LEVEL COMMANDS .............................................................................................................. 35

7.5

VIDEO DECIMATION AND SCALING ................................................................................................ 35

7.6

FREE-RUN AND VBV-BASED DISPLAY SYNCHRONIZATION ............................................................ 37

7.7

MEMORY USAGE REDUCTION ........................................................................................................ 38

7.7.1

Vsync Reset ........................................................................................................................... 38

7.7.2

Split Video Input Buffer......................................................................................................... 39

7.8

CONFIGURATION OF THE VIDEO DECODER..................................................................................... 39

7.8.1

Configuration of video display format ................................................................................. 39

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