TMS320AV7110 datasheet(4/131 Pages) TI

4 / 131 page

DSP

TMS320AV7110

Revision 3.1

10/08/99 22:18

Page 4

13.1.2

The ‘AV7110 writes data to the MPEG2Lynx ....................................................................... 68

13.1.3

The ‘AV7110 Internal Data Path for 1394 ........................................................................... 68

13.2

EXTERNAL DMA INTERFACE......................................................................................................... 70

13.3

IEEE 1284 INTERFACE .................................................................................................................. 72

13.4

COMBINING THE 1394, 1284 AND EXTERNAL CONTROLLER INTERFACES ...................................... 73

14.

COMMUNICATION PROCESSOR............................................................................................. 75

14.1

FEATURES ...................................................................................................................................... 75

14.2

SMART CARD INTERFACE .............................................................................................................. 75

14.3

TIMERS .......................................................................................................................................... 77

14.4

UARTS.......................................................................................................................................... 78

14.5

IR INPUT PORT .............................................................................................................................. 78

14.6

IR OUTPUT PORT ............................................................................................................................ 79

14.7

GENERAL PURPOSE I/OS ................................................................................................................ 80

14.8

2C INTERFACE .............................................................................................................................. 81

15.

DEVICE CONTROL INTERFACES............................................................................................ 82

15.1

RESET ............................................................................................................................................ 82

15.2

JTAG PINS .................................................................................................................................... 82

16.

REGISTER MAPS.......................................................................................................................... 83

16.1

NTSC/PAL REGISTERS - BASE ADDRESS 0X72000000................................................................. 83

16.2

BITBLT REGISTERS - BASE ADDRESS 0X70000000....................................................................... 85

16.3

CCP REGISTERS - BASE ADDRESS 0X6E000000............................................................................ 86

16.4

AUDIO DECODER REGISTERS - BASE ADDRESS 0X6C000000 ........................................................ 94

16.5

VIDEO DECODER REGISTERS - BASE ADDRESS 0X6A000000 ........................................................ 96

16.6

OSD REGISTERS - BASE ADDRESS 0X68000000............................................................................ 99

16.7

TC REGISTERS - BASE ADDRESS 0X66000000............................................................................. 101

16.8

TPP REGISTERS - BASE ADDRESS 0X64000000........................................................................... 105

17.

TIMING DIAGRAMS AND DC PARAMETERS ..................................................................... 108

17.1

DRAM INTERFACE TIMING ......................................................................................................... 109

17.2

EBI INTERFACE TIMING............................................................................................................... 111

17.3

SDRAM INTERFACE TIMING ....................................................................................................... 115

17.4

VIDEO OUTPUT TIMINGS .............................................................................................................. 121

17.5

HSDI TIMING DIAGRAMS ............................................................................................................ 123

17.6

EXTERNAL DMA ......................................................................................................................... 125

17.7

INPUT STREAM TIMING ................................................................................................................ 127

17.8

DC CHARACTERISTICS................................................................................................................. 128

17.9

SDRAM MEMORY MAP FOR FIRST SILICON FIRMWARE .............................................................. 129

17.9.1

PAL mode Memory Map ..................................................................................................... 129

17.9.2

NTSC mode Memory Map ................................................................................................... 130

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