TMS320AV7110 datasheet(10/131 Pages) TI

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DSP

TMS320AV7110

Revision 3.1

10/08/99 22:18

Page 10

Pin Name

I/O

Description

SWE

SDRAM Write Enable

SDOMU

SDRAM Data Mask Enable, Upper byte.

SDOML

SDRAM Data Mask Enable, Lower byte.

SCLK

SDRAM Clock

SCKE

SDRAM Clock Enable

SCS1

SDRAM Chip Select 1

SCS2

SDRAM Chip Select 2

Audio Interface

PCMDATA

PCM Data audio output.

LRCLK

Left/Right Clock for output PCM audio data.

PCMCLK

I /O

PCM Clock (for Input - Note 1).

ASCLK

Audio Serial Data Clock

SPDIF

SPDIF audio output

APLL_LOCK

Remains active while the Internal Audio PLL is stable.

VCXO

CLK27

27 MHz Clock input from an external VCXO (Note 1)

VCXO_CTRL

Digital pulse output for external VCXO Control.

CLK_SEL

Clock select: Low = 27 MHz input clock,

High = 81 MHz input clock.

Digital Video Interface

YCOUT[7:0]

4:2:2 digital video output. (muxed with EXTDATA[7:0])

YCCLK

27 MHz digital video output clock. (muxed with EXTDATA[8])

YCCTRL[1:0]

Digital video output control signals (muxed with EXTDATA[11]

and EXTDATA[10] respectively)

TEXTEN

Teletext window signal - active during Teletext lines. (muxed with

EXTDATA[9])

NTSC/PAL Encoder Interface

VSYNC

I/ O

Vertical synchronization signal

HSYNC

I/ O

Horizontal synchronization signal

OSD_ACTIVE

Active when OSD data is being output on video out (active high)

RC_OUT

Red or C video signal Output.

BIAS_RC

Red or C D/A Bias terminal.

GY_OUT

Green or Y video signal Output.

BIAS_GY

Green or Y D/A Bias terminal.

B_OUT

Blue video signal Output.

BIAS_B

Blue D/A Bias terminal.

Y/COMP_OUT

Composite or Y video signal Output.

BIAS_COMP

Composite Bias terminal.

COMP[3:0]

Compensation-capacitor terminals. [BGRC=3:0]

VREF

Voltage reference.

Device Control

RESET

Reset, active low

TDI

JTAG Data Input. Can be tied high or left floating.

TCK

JTAG Clock. Must be tied low for normal operation.

TMS

JTAG Test Mode Select Can be tied high or left floating.

TRST

JTAG Test Reset, active low. Must be tied low or connected to

RESET for normal operations.

TDO

JTAG Data Output

test

Reserved for Test, tie to ground when not in use

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