MC56F81663 datasheet(10/73 Pages) NXP

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• Programmable length transmissions (2 bits to 16 bits)

• Programmable transmit and receive shift order (MSB or LSB as first bit transmitted)

1.5.12 Low Power Inter-Integrated Circuit (LPI2C)

The LPI2C supports:

• Standard, Fast, Fast+ and Ultra Fast modes are supported

• High speed mode (HS) in slave mode

• High speed mode (HS) in master mode, if SCL pin implements current source pull-

up (device-specific)

• Multi-master support, including synchronization and arbitration. Multi-master means

any number of master nodes can be present. Additionally, master and slave roles may

be changed between messages (after a STOP is sent).

• Clock stretching: Sometimes multiple I2C nodes may be driving the lines at the same

time. If any I2C node is driving a line low, then that line will be low. I2C nodes that

are starting to transmit a logical one (by letting the line float high) can detect that the

line is low, and thereby know that another I2C node is active at the same time.

• When node detection is used on the SCL line, it is called clock stretching, and

clock stretching is used as a I2C flow control mechanism for multiple laves.

• When node detection is used on the SDA line, it is called arbitration, and

arbitration ensures that there is only one I2C node transmitter at a time.

• General call, 7-bit and 10-bit addressing

• Software reset, START byte and Device ID (also require software support)

The LPI2C master supports:

• Command/transmit FIFO of 4words.

• Receive FIFO of 4words.

• Command FIFO will wait for idle I2C bus before initiating transfer

• Command FIFO can initiate (repeated) START and STOP conditions and one or

more master-receiver transfers

• STOP condition can be generated from command FIFO, or generated automatically

when the transmit FIFO is empty

• Host request input to control the start time of an I2C bus transfer

• Flexible receive data match can generate interrupt on data match and/or discard

unwanted data

• Flag and optional interrupt to signal Repeated START condition, STOP condition,

loss of arbitration, unexpected NACK, and command word errors

• Supports configurable bus idle timeout and pin-stuck-low timeout

The LPI2C slave supports:

Peripheral highlights

MC56F81xxx, Rev. 1.1, 12/2020

NXP Semiconductors

MC56F81663 датащи(PDF) 10 Page - NXP Semiconductors