MC56F81663 datasheet(66/73 Pages) NXP

номер детали	MC56F81663

подробное описание детали	DSC based on 32-bit 56800EX core

PDF	73 Pages

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производитель	NXP [NXP Semiconductors]

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SCLK (CPOL = 0)

(Input)

SCLK (CPOL = 1)

(Input)

MISO

(Output)

MOSI

(Input)

Slave MSB out

Bits 14–1

tCL

tCH

tDI

MSB in

Bits 14–1

LSB in

(Input)

tCH

tDH

Slave LSB out

tELD

tDV

tELG

tDV

tDS

Figure 19. SPI slave timing (CPHA = 1)

11.7.2 Queued Serial Communication Interface (SCI) timing

Parameters listed are guaranteed by design.

Table 36. SCI timing

Characteristic

Symbol

Min

Max

Unit

See Figure

Baud rate1

—

(fMAX/16)

Mbit/s

—

RXD pulse width

RXDPW

0.965/BR

1.04/BR

μs

Figure 20

TXD pulse width

TXDPW

0.965/BR

1.04/BR

μs

Figure 21

LIN Slave Mode

Deviation of slave node clock from nominal

clock rate before synchronization

FTOL_UNSYNCH

-14

—

Deviation of slave node clock relative to

the master node clock after

synchronization

FTOL_SYNCH

-2

—

Minimum break character length

TBREAK

—

Master

node bit

periods

—

Slave node

bit periods

—

1. fMAX is the frequency of operation of the SCI clock in MHz, which can be selected as the bus clock (max.50 MHz

depending on part number) or 2x bus clock (max. 100 MHz) for the devices.

PWMs and timers

MC56F81xxx, Rev. 1.1, 12/2020

NXP Semiconductors

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