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MC56F81663 датащи(PDF) 14 Page - NXP Semiconductors |
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MC56F81663 датащи(HTML) 14 Page - NXP Semiconductors |
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14 / 73 page ![]() EOnCE 56800EX CPU Program Bus Core Data Bus Secondary Data Bus Program/Data Flash Up to 128 KB Data/Program RAM Up to 20 KB Interrupt Controller QSCI 0,1 QSPI LPI2C 0,1 Quad Timer 4ch eFlexPWM NanoEdge ADCA 12Bit ADCB 12Bit Compartors With 8bit DAC A,B,C,D Watchdog (COP) EWM CRC DAC 12Bit Event Generator Inter-Module Crossbar Inter Module connection GPIO & Peripheral MUX Crystal OSC Internal IRC 2 MHz/ 8 MHz Internal IRC 200 kHz PLL Power Management Controller (PMC) System Integration Module (SIM) Package Pins Peripheral Bus Peripheral Bus 4 JTAG Inter Module Crossbar Inputs Inter Module Crossbar Outputs Program Controller (PC) Address Generation Unit (AGU) Arithmetic Logic Unit (ALU) Bit Manipulation Unit Inter Module Crossbar Outputs Inter Module Crossbar Inputs M0 M1 M2 S0 S1 S2 S3 Op-Amp 0.1 Boot ROM 32 KB eDMA Controller M3 Periodic Interrupt Timer (PIT32) 0,1 Quadrature Decoder ROM Patch Controller Figure 1. System block diagram Clock sources MC56F81xxx, Rev. 1.1, 12/2020 14 NXP Semiconductors |
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