MC56F81663 datasheet(70/73 Pages) NXP

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• Consider all device loads as well as parasitic capacitance due to PCB traces when

calculating capacitance. This is especially critical in systems with higher capacitive

loads that could create higher transient currents in the VDD and VSS circuits.

• Take special care to minimize noise levels on the VREF, VDDA, and VSSA pins.

• Using separate power planes for VDD and VDDA and separate ground planes for VSS

and VSSA are recommended. Connect the separate analog and digital power and

ground planes as near as possible to power supply outputs. If an analog circuit and

digital circuit are powered by the same power supply, then connect a small inductor

or ferrite bead in serial with VDDA. Traces of VSS and VSSA should be shorted

together.

• Physically separate analog components from noisy digital components by ground

planes. Do not place an analog trace in parallel with digital traces. Place an analog

ground trace around an analog signal trace to isolate it from digital traces.

• Because the flash memory is programmed through the JTAG/EOnCE port, SPI, SCI,

or I2C, the designer should provide an interface to this port if in-circuit flash

programming is desired.

• If desired, connect an external RC circuit to the RESET pin. The resistor value

should be in the range of 4.7 kΩ–10 kΩ; the capacitor value should be in the range of

0.1 µF–4.7 µF.

• Configuring the RESET pin to GPIO output in normal operation in a high-noise

environment may help to improve the performance of noise transient immunity.

• Add a 2.2 kΩ external pullup on the TMS pin of the JTAG port to keep EOnCE in a

reset state during normal operation if JTAG converter is not present. Furthermore,

configure TMS, TDI, TDO and TCK to GPIO if operation environment is very noisy.

• During reset and after reset but before I/O initialization, all the GPIO pins are at tri-

state.

• To eliminate PCB trace impedance effect, each ADC input should have a no less than

33 pF 10Ω RC filter.

12.3 Power-on Reset design considerations

12.3.1 Improper power-up sequence between VDD/VSS and VDDA/

VSSA:

It is recommended that VDD be kept within 100 mV of VDDA at all times, including

power ramp-up and ramp-down. Failure to keep VDD within 100 mV of VDDA may

cause a leakage current through the substrate, between the VDD and VDDA pad cells.

This leakage current could prevent operation of the device after it powers up. The voltage

Design Considerations

MC56F81xxx, Rev. 1.1, 12/2020

NXP Semiconductors

MC56F81663 датащи(PDF) 70 Page - NXP Semiconductors