MC56F81663 datasheet(71/73 Pages) NXP

71 / 73 page

difference between VDD and VDDA must be limited to below 0.3 V at all times, to avoid

permanent damage to the part (See the table in "Voltage and current operating ratings"

section). Also see the table in "Voltage and current operating requirements" section.

12.3.2 Heavy capacitive load on power supply output:

In some applications, the low cost DC/DC converter may not regulate the output voltage

well before it reaches the regulation point, which is roughly around 2.5V to 2.7V.

However, the device might exit power-on reset at around 2.3V. If the initialization code

enables the PLL to run the DSC at full speed right after reset, then the high current will

be pulled by DSC from the supply, which can cause the supply voltage to drop below the

operation voltage; see the captured graph (Figure 22). This can cause the DSC fail to start

up.

Figure 22. Supply Voltage Drop

A recommended initialization sequence during power-up is:

1. After POR is released, run a few hundred NOP instructions from the internal

relaxation oscillator; this gives time for the supply voltage to stabilize.

2. Configure the peripherals (except the ADC) to the desired settings; the ADC should

stay in low power mode.

3. Power up the PLL.

4. After the PLL locks, switch the clock from PLL prescale to postscale.

5. Configure the ADC.

13 Obtaining package dimensions

Package dimensions are provided in package drawings.

Obtaining package dimensions

MC56F81xxx, Rev. 1.1, 12/2020

NXP Semiconductors

MC56F81663 датащи(PDF) 71 Page - NXP Semiconductors