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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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MC56F81663 датащи(PDF) 15 Page - NXP Semiconductors |
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MC56F81663 датащи(HTML) 15 Page - NXP Semiconductors |
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15 / 73 page  2 MC56F81xxx signal and pin descriptions After reset, each pin is configured for its primary function (listed first). Any alternative functionality, shown in parentheses, must be programmed through the GPIO module peripheral enable registers (GPIOx_PER) and the SIM module GPIO peripheral select (GPSx) registers. All GPIO ports can be individually programmed as an input or output (using bit manipulation). For the MC56F81xxx products, which use 64-pin LQFP, 48-pin LQFP and 32-pin LQFP packages: Table 2. Signal descriptions Signal Name 64 LQFP 48 LQFP 32 LQFP/ QFN State During Reset Type Signal Description VDD 29 — — Supply Supply I/O Power — Supplies 3.3 V power to the chip I/O interface. 44 32 — 60 44 28 VSS 30 22 14 Supply Supply I/O Ground — Provide ground for the device I/O interface. 43 31 — 61 45 29 VDDA 22 15 9 Supply Supply Analog Power — Supplies 3.3 V power to the analog modules. It must be connected to a clean analog power supply. VSSA 23 16 10 Supply Supply Analog Ground — Supplies an analog ground to the analog modules. It must be connected to a clean power supply. VCAP 26 19 — On-chip regulator output On-chip regulator output Connect a 2.2 µF or greater bypass capacitor between this pin and VSS to stabilize the core voltage regulator output required for proper device operation. NOTE: The total bypass capacitor value between all VCAP pins and VSS recommends between 4.0uF ~ 5.0uF. 57 43 27 TDI 64 48 32 Input, internal pullup enabled Input Test Data Input — Provides a serial input data stream to the JTAG/EOnCE port. It is sampled on the rising edge of TCK and has an internal pullup resistor. After reset, the default state is TDI. (GPIOD0) Input/ Output GPIO Port D0. TDO 62 46 30 Output Output Test Data Output — This tri-state-able pin provides a serial output data stream from the JTAG/EOnCE port. It is driven in the shift-IR and shift-DR controller states, and it changes on the falling edge of TCK. After reset, the default state is TDO. (GPIOD1) Input/ Output GPIO Port D1. Table continues on the next page... MC56F81xxx signal and pin descriptions MC56F81xxx, Rev. 1.1, 12/2020 NXP Semiconductors 15 |
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