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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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ATMEGA640 датащи(PDF) 152 Page - Microchip Technology |
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ATMEGA640 датащи(HTML) 152 Page - Microchip Technology |
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152 / 436 page  152 ATmega640/V-1280/V-1281/V-2560/V-2561/V [DATASHEET] DS40002211A 17.10 Timer/Counter Timing Diagrams The Timer/Counter is a synchronous design and the timer clock (clkTn) is therefore shown as a clock enable signal in the following figures. The figures include information on when Interrupt Flags are set, and when the OCRnx Reg- ister is updated with the OCRnx buffer value (only for modes utilizing double buffering). Figure 17-10 shows a timing diagram for the setting of OCFnx. Figure 17-10. Timer/Counter Timing Diagram, Setting of OCFnx, no Prescaling Figure 17-11 shows the same timing data, but with the prescaler enabled. Figure 17-11. Timer/Counter Timing Diagram, Setting of OCFnx, with Prescaler (fclk_I/O/8) clk Tn (clk I/O/1) OCFnx clk I/O OCRnx TCNTn OCRnx Value OCRnx - 1 OCRnx OCRnx + 1 OCRnx + 2 OCFnx OCRnx TCNTn OCRnx Value OCRnx - 1 OCRnx OCRnx + 1 OCRnx + 2 clk I/O clk Tn (clk I/O/8) |
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