ATMEGA640 datasheet(149/436 Pages) MICROCHIP

149 / 436 page

149

ATmega640/V-1280/V-1281/V-2560/V-2561/V [DATASHEET]

DS40002211A

on Figure 17-8 on page 149. The figure shows phase correct PWM mode when OCRnA or ICRn is used to define

TOP. The TCNTn value is in the timing diagram shown as a histogram for illustrating the dual-slope operation. The

diagram includes non-inverted and inverted PWM outputs. The small horizontal line marks on the TCNTn slopes

represent compare matches between OCRnx and TCNTn. The OCnx Interrupt Flag will be set when a compare

match occurs.

Figure 17-8. Phase Correct PWM Mode, Timing Diagram

The Timer/Counter Overflow Flag (TOVn) is set each time the counter reaches BOTTOM. When either OCRnA or

ICRn is used for defining the TOP value, the OCnA or ICFn Flag is set accordingly at the same timer clock cycle as

the OCRnx Registers are updated with the double buffer value (at TOP). The Interrupt Flags can be used to gener-

ate an interrupt each time the counter reaches the TOP or BOTTOM value.

When changing the TOP value the program must ensure that the new TOP value is higher or equal to the value of

all of the Compare Registers. If the TOP value is lower than any of the Compare Registers, a compare match will

never occur between the TCNTn and the OCRnx. Note that when using fixed TOP values, the unused bits are

masked to zero when any of the OCRnx Registers are written. As the third period shown in Figure 17-8 illustrates,

changing the TOP actively while the Timer/Counter is running in the phase correct mode can result in an unsym-

metrical output. The reason for this can be found in the time of update of the OCRnx Register. Since the OCRnx

update occurs at TOP, the PWM period starts and ends at TOP. This implies that the length of the falling slope is

determined by the previous TOP value, while the length of the rising slope is determined by the new TOP value.

When these two values differ the two slopes of the period will differ in length. The difference in length gives the

unsymmetrical result on the output.

It is recommended to use the phase and frequency correct mode instead of the phase correct mode when chang-

ing the TOP value while the Timer/Counter is running. When using a static TOP value there are practically no

differences between the two modes of operation.

In phase correct PWM mode, the compare units allow generation of PWM waveforms on the OCnx pins. Setting

the COMnx1:0 bits to two will produce a non-inverted PWM and an inverted PWM output can be generated by set-

ting the COMnx1:0 to three (see Table 17-5 on page 155). The actual OCnx value will only be visible on the port

pin if the data direction for the port pin is set as output (DDR_OCnx). The PWM waveform is generated by setting

(or clearing) the OCnx Register at the compare match between OCRnx and TCNTn when the counter increments,

and clearing (or setting) the OCnx Register at compare match between OCRnx and TCNTn when the counter dec-

OCRnx/TOP Update and

OCnA Interrupt Flag Set

or ICFn Interrupt Flag Set

(Interrupt on TOP)

TOVn Interrupt Flag Set

(Interrupt on Bottom)

TCNTn

Period

OCnx

(COMnx1:0 = 2)

(COMnx1:0 = 3)

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