ATMEGA640 datasheet(150/436 Pages) MICROCHIP

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ATmega640/V-1280/V-1281/V-2560/V-2561/V [DATASHEET]

DS40002211A

rements. The PWM frequency for the output when using phase correct PWM can be calculated by the following

equation:

The N variable represents the prescaler divider (1, 8, 64, 256, or 1024).

The extreme values for the OCRnx Register represent special cases when generating a PWM waveform output in

the phase correct PWM mode. If the OCRnx is set equal to BOTTOM the output will be continuously low and if set

equal to TOP the output will be continuously high for non-inverted PWM mode. For inverted PWM the output will

have the opposite logic values. If OCR1A is used to define the TOP value (WGM13:0 = 11) and COM1A1:0 = 1, the

OC1A output will toggle with a 50% duty cycle.

17.9.5

Phase and Frequency Correct PWM Mode

The phase and frequency correct Pulse Width Modulation, or phase and frequency correct PWM mode (WGMn3:0

= 8 or 9) provides a high resolution phase and frequency correct PWM waveform generation option. The phase

and frequency correct PWM mode is, like the phase correct PWM mode, based on a dual-slope operation. The

counter counts repeatedly from BOTTOM (0x0000) to TOP and then from TOP to BOTTOM. In non-inverting Com-

pare Output mode, the Output Compare (OCnx) is cleared on the compare match between TCNTn and OCRnx

while upcounting, and set on the compare match while downcounting. In inverting Compare Output mode, the

operation is inverted. The dual-slope operation gives a lower maximum operation frequency compared to the sin-

gle-slope operation. However, due to the symmetric feature of the dual-slope PWM modes, these modes are

preferred for motor control applications.

The main difference between the phase correct, and the phase and frequency correct PWM mode is the time the

OCRnx Register is updated by the OCRnx Buffer Register, see Figure 17-8 on page 149 and Figure 17-9 on page

151.

The PWM resolution for the phase and frequency correct PWM mode can be defined by either ICRn or OCRnA.

The minimum resolution allowed is 2-bit (ICRn or OCRnA set to 0x0003), and the maximum resolution is 16-bit

(ICRn or OCRnA set to MAX). The PWM resolution in bits can be calculated using the following equation:

In phase and frequency correct PWM mode the counter is incremented until the counter value matches either the

value in ICRn (WGMn3:0 = 8), or the value in OCRnA (WGMn3:0 = 9). The counter has then reached the TOP and

changes the count direction. The TCNTn value will be equal to TOP for one timer clock cycle. The timing diagram

for the phase correct and frequency correct PWM mode is shown on Figure 17-9 on page 151. The figure shows

phase and frequency correct PWM mode when OCRnA or ICRn is used to define TOP. The TCNTn value is in the

timing diagram shown as a histogram for illustrating the dual-slope operation. The diagram includes non-inverted

and inverted PWM outputs. The small horizontal line marks on the TCNTn slopes represent compare matches

between OCRnx and TCNTn. The OCnx Interrupt Flag will be set when a compare match occurs.

fOCnxPCPWM

fclk_I/O

2 NTOP



----------------------------

RPFCPWM

TOP 1



log



log

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