ATMEGA640 datasheet(65/436 Pages) MICROCHIP

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ATmega640/V-1280/V-1281/V-2560/V-2561/V [DATASHEET]

DS40002211A

12.5.2

WDTCSR – Watchdog Timer Control Register

• Bit 7 - WDIF: Watchdog Interrupt Flag

This bit is set when a time-out occurs in the Watchdog Timer and the Watchdog Timer is configured for interrupt.

WDIF is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, WDIF is

cleared by writing a logic one to the flag. When the I-bit in SREG and WDIE are set, the Watchdog Time-out Inter-

rupt is executed.

• Bit 6 - WDIE: Watchdog Interrupt Enable

When this bit is written to one and the I-bit in the Status Register is set, the Watchdog Interrupt is enabled. If WDE

is cleared in combination with this setting, the Watchdog Timer is in Interrupt Mode, and the corresponding inter-

rupt is executed if time-out in the Watchdog Timer occurs.

If WDE is set, the Watchdog Timer is in Interrupt and System Reset Mode. The first time-out in the Watchdog

Timer will set WDIF. Executing the corresponding interrupt vector will clear WDIE and WDIF automatically by hard-

ware (the Watchdog goes to System Reset Mode). This is useful for keeping the Watchdog Timer security while

using the interrupt. To stay in Interrupt and System Reset Mode, WDIE must be set after each interrupt. This

should however not be done within the interrupt service routine itself, as this might compromise the safety-function

of the Watchdog System Reset mode. If the interrupt is not executed before the next time-out, a System Reset will

be applied.

Note:

1. WDTON Fuse set to “0“ means programmed and “1” means unprogrammed.

• Bit 4 - WDCE: Watchdog Change Enable

This bit is used in timed sequences for changing WDE and prescaler bits. To clear the WDE bit, and/or change the

prescaler bits, WDCE must be set.

Once written to one, hardware will clear WDCE after four clock cycles.

• Bit 3 - WDE: Watchdog System Reset Enable

WDE is overridden by WDRF in MCUSR. This means that WDE is always set when WDRF is set. To clear WDE,

WDRF must be cleared first. This feature ensures multiple resets during conditions causing failure, and a safe

start-up after the failure.

• Bit 5, 2:0 - WDP3:0: Watchdog Timer Prescaler 3, 2, 1 and 0

The WDP3:0 bits determine the Watchdog Timer prescaling when the Watchdog Timer is running. The different

prescaling values and their corresponding time-out periods are shown in Table 12-2 on page 66.

Bit

(0x60)

WDIF

WDIE

WDP3

WDCE

WDE

WDP2

WDP1

WDP0

WDTCSR

Read/Write

R/W

R/WR/W

Initial Value

Table 12-1.

Watchdog Timer Configuration

WDTON(1)

WDE

WDIE

Mode

Action on Time-out

Stopped

None

Interrupt Mode

Interrupt

System Reset Mode

Reset

Interrupt and System Reset Mode

Interrupt, then go to System Reset Mode

System Reset Mode

Reset

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