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ATMEGA640 датащи(PDF) 30 Page - Microchip Technology |
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ATMEGA640 датащи(HTML) 30 Page - Microchip Technology |
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30 / 436 page ![]() 30 ATmega640/V-1280/V-1281/V-2560/V-2561/V [DATASHEET] DS40002211A Figure 9-4. External Data Memory Cycles with SRWn1 = 0 and SRWn0 = 1(1) Note: 1. SRWn1 = SRW11 (upper sector) or SRW01 (lower sector), SRWn0 = SRW10 (upper sector) or SRW00 (lower sec- tor). The ALE pulse in period T5 is only present if the next instruction accesses the RAM (internal or external). Figure 9-5. External Data Memory Cycles with SRWn1 = 1 and SRWn0 = 0(1) Note: 1. SRWn1 = SRW11 (upper sector) or SRW01 (lower sector), SRWn0 = SRW10 (upper sector) or SRW00 (lower sec- tor). The ALE pulse in period T6 is only present if the next instruction accesses the RAM (internal or external). ALE T1 T2 T3 WR T5 A15:8 Address Prev. addr. DA7:0 Address Data Prev. data XX RD DA7:0 (XMBK = 0) Data Prev. data Address Data Prev. data Address DA7:0 (XMBK = 1) System Clock (CLKCPU) T4 ALE T1 T2 T3 WR T6 A15:8 Address Prev. addr. DA7:0 Address Data Prev. data XX RD DA7:0 (XMBK = 0) Data Prev. data Address Data Prev. data Address DA7:0 (XMBK = 1) System Clock (CLKCPU) T4 T5 |
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