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ATMEGA640 датащи(PDF) 81 Page - Microchip Technology |
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ATMEGA640 датащи(HTML) 81 Page - Microchip Technology |
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81 / 436 page ![]() 81 ATmega640/V-1280/V-1281/V-2560/V-2561/V [DATASHEET] DS40002211A •INT3/TXD1 – Port D, Bit 3 INT3, External Interrupt source 3: The PD3 pin can serve as an external interrupt source to the MCU. TXD1, Transmit Data (Data output pin for the USART1). When the USART1 Transmitter is enabled, this pin is con- figured as an output regardless of the value of DDD3. •INT2/RXD1 – Port D, Bit 2 INT2, External Interrupt source 2. The PD2 pin can serve as an External Interrupt source to the MCU. RXD1, Receive Data (Data input pin for the USART1). When the USART1 receiver is enabled this pin is configured as an input regardless of the value of DDD2. When the USART forces this pin to be an input, the pull-up can still be controlled by the PORTD2 bit. •INT1/SDA – Port D, Bit 1 INT1, External Interrupt source 1. The PD1 pin can serve as an external interrupt source to the MCU. SDA, 2-wire Serial Interface Data: When the TWEN bit in TWCR is set (one) to enable the 2-wire Serial Interface, pin PD1 is disconnected from the port and becomes the Serial Data I/O pin for the 2-wire Serial Interface. In this mode, there is a spike filter on the pin to suppress spikes shorter than 50ns on the input signal, and the pin is driven by an open drain driver with slew-rate limitation. •INT0/SCL – Port D, Bit 0 INT0, External Interrupt source 0. The PD0 pin can serve as an external interrupt source to the MCU. SCL, 2-wire Serial Interface Clock: When the TWEN bit in TWCR is set (one) to enable the 2-wire Serial Interface, pin PD0 is disconnected from the port and becomes the Serial Clock I/O pin for the 2-wire Serial Interface. In this mode, there is a spike filter on the pin to suppress spikes shorter than 50ns on the input signal, and the pin is driven by an open drain driver with slew-rate limitation. Table 13-13 on page 81 and Table 13-14 on page 82 relates the alternate functions of Port D to the overriding sig- nals shown in Figure 13-5 on page 73. Table 13-13. Overriding Signals for Alternate Functions PD7:PD4 Signal Name PD7/T0 PD6/T1 PD5/XCK1 PD4/ICP1 PUOE 0 0 0 0 PUOV 0 0 0 0 DDOE 0 0 XCK1 OUTPUT ENABLE 0 DDOV 0 0 1 0 PVOE 0 0 XCK1 OUTPUT ENABLE 0 PVOV 0 0 XCK1 OUTPUT 0 DIEOE 0 0 0 0 DIEOV 0 0 0 0 DI T0 INPUT T1 INPUT XCK1 INPUT ICP1 INPUT AIO – – – – |
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