ATMEGA640 datasheet(57/436 Pages) MICROCHIP

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ATmega640/V-1280/V-1281/V-2560/V-2561/V [DATASHEET]

DS40002211A

12. System Control and Reset

12.1 Resetting the AVR

During reset, all I/O Registers are set to their initial values, and the program starts execution from the Reset Vec-

tor. The instruction placed at the Reset Vector must be a JMP – Absolute Jump – instruction to the reset handling

routine. If the program never enables an interrupt source, the Interrupt Vectors are not used, and regular program

code can be placed at these locations. This is also the case if the Reset Vector is in the Application section while

the Interrupt Vectors are in the Boot section or vice versa. The circuit diagram in Figure 12-1 on page 58 shows the

reset logic. “System and Reset Characteristics” on page 360 defines the electrical parameters of the reset circuitry.

The I/O ports of the AVR are immediately reset to their initial state when a reset source goes active. This does not

require any clock source to be running.

After all reset sources have gone inactive, a delay counter is invoked, stretching the internal reset. This allows the

power to reach a stable level before normal operation starts. The time-out period of the delay counter is defined by

the user through the SUT and CKSEL Fuses. The different selections for the delay period are presented in “Clock

Sources” on page 40.

12.2 Reset Sources

The ATmega640/1280/1281/2560/2561 has five sources of reset:

•

Power-on Reset. The MCU is reset when the supply voltage is below the Power-on Reset threshold (VPOT)

•

External Reset. The MCU is reset when a low level is present on the RESET pin for longer than the minimum

pulse length

•

Watchdog Reset. The MCU is reset when the Watchdog Timer period expires and the Watchdog is enabled

•

Brown-out Reset. The MCU is reset when the supply voltage AVCC is below the Brown-out Reset threshold

(VBOT) and the Brown-out Detector is enabled

•

JTAG AVR Reset. The MCU is reset as long as there is a logic one in the Reset Register, one of the scan

chains of the JTAG system. Refer to the section “IEEE 1149.1 (JTAG) Boundary-scan” on page 295 for details

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