ATMEGA640 datasheet(148/436 Pages) MICROCHIP

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ATmega640/V-1280/V-1281/V-2560/V-2561/V [DATASHEET]

DS40002211A

the TCNTn matches TOP. The update is done at the same timer clock cycle as the TCNTn is cleared and the

TOVn Flag is set.

Using the ICRn Register for defining TOP works well when using fixed TOP values. By using ICRn, the OCRnA

changed (by changing the TOP value), using the OCRnA as TOP is clearly a better choice due to its double buffer

feature.

In fast PWM mode, the compare units allow generation of PWM waveforms on the OCnx pins. Setting the COM-

nx1:0 bits to two will produce a non-inverted PWM and an inverted PWM output can be generated by setting the

COMnx1:0 to three (see Table on page 155). The actual OCnx value will only be visible on the port pin if the data

direction for the port pin is set as output (DDR_OCnx). The PWM waveform is generated by setting (or clearing)

the OCnx Register at the compare match between OCRnx and TCNTn, and clearing (or setting) the OCnx Register

at the timer clock cycle the counter is cleared (changes from TOP to BOTTOM).

The PWM frequency for the output can be calculated by the following equation:

The N variable represents the prescaler divider (1, 8, 64, 256, or 1024).

The extreme values for the OCRnx Register represents special cases when generating a PWM waveform output in

the fast PWM mode. If the OCRnx is set equal to BOTTOM (0x0000) the output will be a narrow spike for each

TOP+1 timer clock cycle. Setting the OCRnx equal to TOP will result in a constant high or low output (depending

on the polarity of the output set by the COMnx1:0 bits).

A frequency (with 50% duty cycle) waveform output in fast PWM mode can be achieved by setting OCnA to toggle

its logical level on each compare match (COMnA1:0 = 1). This applies only if OCR1A is used to define the TOP

value (WGM13:0 = 15). The waveform generated will have a maximum frequency of fOCnA = fclk_I/O/2 when OCRnA

is set to zero (0x0000). This feature is similar to the OCnA toggle in CTC mode, except the double buffer feature of

the Output Compare unit is enabled in the fast PWM mode.

17.9.4

Phase Correct PWM Mode

The phase correct Pulse Width Modulation or phase correct PWM mode (WGMn3:0 = 1, 2, 3, 10, or 11) provides a

high resolution phase correct PWM waveform generation option. The phase correct PWM mode is, like the phase

and frequency correct PWM mode, based on a dual-slope operation. The counter counts repeatedly from BOT-

TOM (0x0000) to TOP and then from TOP to BOTTOM. In non-inverting Compare Output mode, the Output

Compare (OCnx) is cleared on the compare match between TCNTn and OCRnx while upcounting, and set on the

compare match while downcounting. In inverting Output Compare mode, the operation is inverted. The dual-slope

operation has lower maximum operation frequency than single slope operation. However, due to the symmetric

feature of the dual-slope PWM modes, these modes are preferred for motor control applications.

The PWM resolution for the phase correct PWM mode can be fixed to 8-bit, 9-bit, or 10-bit, or defined by either

ICRn or OCRnA. The minimum resolution allowed is 2-bit (ICRn or OCRnA set to 0x0003), and the maximum res-

olution is 16-bit (ICRn or OCRnA set to MAX). The PWM resolution in bits can be calculated by using the following

equation:

In phase correct PWM mode the counter is incremented until the counter value matches either one of the fixed val-

ues 0x00FF, 0x01FF, or 0x03FF (WGMn3:0 = 1, 2, or 3), the value in ICRn (WGMn3:0 = 10), or the value in

OCRnA (WGMn3:0 = 11). The counter has then reached the TOP and changes the count direction. The TCNTn

value will be equal to TOP for one timer clock cycle. The timing diagram for the phase correct PWM mode is shown

fOCnxPWM

fclk_I/O

1 TOP





-----------------------------------

RPCPWM

TOP 1



log



log

-----------------------------------

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