ATMEGA640 datasheet(121/436 Pages) MICROCHIP

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ATmega640/V-1280/V-1281/V-2560/V-2561/V [DATASHEET]

DS40002211A

For generating a waveform output in CTC mode, the OC0A output can be set to toggle its logical level on each

Compare Match by setting the Compare Output mode bits to toggle mode (COM0A1:0 = 1). The OC0A value will

not be visible on the port pin unless the data direction for the pin is set to output. The waveform generated will have

a maximum frequency of fOC0 = fclk_I/O/2 when OCR0A is set to zero (0x00). The waveform frequency is defined by

the following equation:

The N variable represents the prescale factor (1, 8, 64, 256, or 1024).

As for the Normal mode of operation, the TOV0 Flag is set in the same timer clock cycle that the counter counts

from MAX to 0x00.

16.7.3

Fast PWM Mode

The fast Pulse Width Modulation or fast PWM mode (WGM02:0 = 3 or 7) provides a high frequency PWM wave-

form generation option. The fast PWM differs from the other PWM option by its single-slope operation. The counter

counts from BOTTOM to TOP then restarts from BOTTOM. TOP is defined as 0xFF when WGM2:0 = 3, and

OCR0A when WGM2:0 = 7. In non-inverting Compare Output mode, the Output Compare (OC0x) is cleared on the

Compare Match between TCNT0 and OCR0x, and set at BOTTOM. In inverting Compare Output mode, the output

is set on Compare Match and cleared at BOTTOM. Due to the single-slope operation, the operating frequency of

the fast PWM mode can be twice as high as the phase correct PWM mode that use dual-slope operation. This high

frequency makes the fast PWM mode well suited for power regulation, rectification, and DAC applications. High

frequency allows physically small sized external components (coils, capacitors), and therefore reduces total sys-

tem cost.

In fast PWM mode, the counter is incremented until the counter value matches the TOP value. The counter is then

cleared at the following timer clock cycle. The timing diagram for the fast PWM mode is shown in Figure 16-6. The

TCNT0 value is in the timing diagram shown as a histogram for illustrating the single-slope operation. The diagram

includes non-inverted and inverted PWM outputs. The small horizontal line marks on the TCNT0 slopes represent

Compare Matches between OCR0x and TCNT0.

Figure 16-6. Fast PWM Mode, Timing Diagram

fOCnx

fclk_I/O

2 N

1 OCRnx





--------------------------------------------------

TCNTn

OCRnx Update and

TOVn Interrupt Flag Set

Period

OCnx

(COMnx1:0 = 2)

(COMnx1:0 = 3)

OCRnx Interrupt Flag Set

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