ATMEGA640 datasheet(117/436 Pages) MICROCHIP

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ATmega640/V-1280/V-1281/V-2560/V-2561/V [DATASHEET]

DS40002211A

Figure 16-2. Counter Unit Block Diagram

Signal description (internal signals):

count

Increment or decrement TCNT0 by 1.

direction

Select between increment and decrement.

clear

Clear TCNT0 (set all bits to zero).

clkTn

Timer/Counter clock, referred to as clkT0 in the following.

top

Signalize that TCNT0 has reached maximum value.

bottom

Signalize that TCNT0 has reached minimum value (zero).

Depending of the mode of operation used, the counter is cleared, incremented, or decremented at each timer clock

(clkT0). clkT0 can be generated from an external or internal clock source, selected by the Clock Select bits

(CS02:0). When no clock source is selected (CS02:0 = 0) the timer is stopped. However, the TCNT0 value can be

accessed by the CPU, regardless of whether clkT0 is present or not. A CPU write overrides (has priority over) all

counter clear or count operations.

The counting sequence is determined by the setting of the WGM01 and WGM00 bits located in the Timer/Counter

Control Register (TCCR0A) and the WGM02 bit located in the Timer/Counter Control Register B (TCCR0B). There

are close connections between how the counter behaves (counts) and how waveforms are generated on the Out-

put Compare outputs OC0A and OC0B. For more details about advanced counting sequences and waveform

generation, see “Modes of Operation” on page 120.

The Timer/Counter Overflow Flag (TOV0) is set according to the mode of operation selected by the WGM02:0 bits.

TOV0 can be used for generating a CPU interrupt.

16.5 Output Compare Unit

The 8-bit comparator continuously compares TCNT0 with the Output Compare Registers (OCR0A and OCR0B).

Whenever TCNT0 equals OCR0A or OCR0B, the comparator signals a match. A match will set the Output Com-

pare Flag (OCF0A or OCF0B) at the next timer clock cycle. If the corresponding interrupt is enabled, the Output

Compare Flag generates an Output Compare interrupt. The Output Compare Flag is automatically cleared when

the interrupt is executed. Alternatively, the flag can be cleared by software by writing a logical one to its I/O bit loca-

tion. The Waveform Generator uses the match signal to generate an output according to operating mode set by the

WGM02:0 bits and Compare Output mode (COM0x1:0) bits. The maximum and bottom signals are used by the

Waveform Generator for handling the special cases of the extreme values in some modes of operation (“Modes of

Operation” on page 120).

Figure 16-3 on page 118 shows a block diagram of the Output Compare unit.

DATA BUS

TCNTn

Control Logic

count

TOVn

(Int.Req.)

Clock Select

top

Edge

Detector

( From Prescaler )

clk

bottom

direction

clear

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