ATMEGA640 datasheet(120/436 Pages) MICROCHIP

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ATmega640/V-1280/V-1281/V-2560/V-2561/V [DATASHEET]

DS40002211A

16.7 Modes of Operation

The mode of operation, that is, the behavior of the Timer/Counter and the Output Compare pins, is defined by the

combination of the Waveform Generation mode (WGM02:0) and Compare Output mode (COM0x1:0) bits. The

Compare Output mode bits do not affect the counting sequence, while the Waveform Generation mode bits do.

The COM0x1:0 bits control whether the PWM output generated should be inverted or not (inverted or non-inverted

PWM). For non-PWM modes the COM0x1:0 bits control whether the output should be set, cleared, or toggled at a

Compare Match. See “Compare Match Output Unit” on page 143.

For detailed timing information see “Timer/Counter Timing Diagrams” on page 124.

16.7.1

Normal Mode

The simplest mode of operation is the Normal mode (WGM02:0 = 0). In this mode the counting direction is always

up (incrementing), and no counter clear is performed. The counter simply overruns when it passes its maximum 8-

bit value (TOP = 0xFF) and then restarts from the bottom (0x00). In normal operation the Timer/Counter Overflow

Flag (TOV0) will be set in the same timer clock cycle as the TCNT0 becomes zero. The TOV0 Flag in this case

behaves like a ninth bit, except that it is only set, not cleared. However, combined with the timer overflow interrupt

that automatically clears the TOV0 Flag, the timer resolution can be increased by software. There are no special

cases to consider in the Normal mode, a new counter value can be written anytime.

The Output Compare Unit can be used to generate interrupts at some given time. Using the Output Compare to

generate waveforms in Normal mode is not recommended, since this will occupy too much of the CPU time.

16.7.2

Clear Timer on Compare Match (CTC) Mode

In Clear Timer on Compare or CTC mode (WGM02:0 = 2), the OCR0A Register is used to manipulate the counter

resolution. In CTC mode the counter is cleared to zero when the counter value (TCNT0) matches the OCR0A. The

OCR0A defines the top value for the counter, hence also its resolution. This mode allows greater control of the

Compare Match output frequency. It also simplifies the operation of counting external events.

The timing diagram for the CTC mode is shown in Figure 16-5. The counter value (TCNT0) increases until a Com-

pare Match occurs between TCNT0 and OCR0A, and then counter (TCNT0) is cleared.

Figure 16-5. CTC Mode, Timing Diagram

An interrupt can be generated each time the counter value reaches the TOP value by using the OCF0A Flag. If the

interrupt is enabled, the interrupt handler routine can be used for updating the TOP value. However, changing TOP

to a value close to BOTTOM when the counter is running with none or a low prescaler value must be done with

care since the CTC mode does not have the double buffering feature. If the new value written to OCR0A is lower

than the current value of TCNT0, the counter will miss the Compare Match. The counter will then have to count to

its maximum value (0xFF) and wrap around starting at 0x00 before the Compare Match can occur.

TCNTn

OCn

(Toggle)

OCnx Interrupt Flag Set

Period

(COMnx1:0 = 1)

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