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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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ATMEGA640 датащи(PDF) 113 Page - Microchip Technology |
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ATMEGA640 датащи(HTML) 113 Page - Microchip Technology |
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113 / 436 page  113 ATmega640/V-1280/V-1281/V-2560/V-2561/V [DATASHEET] DS40002211A 15.2.6 PCIFR – Pin Change Interrupt Flag Register • Bit 2 – PCIF2: Pin Change Interrupt Flag 1 When a logic change on any PCINT23:16 pin triggers an interrupt request, PCIF2 becomes set (one). If the I-bit in SREG and the PCIE2 bit in PCICR are set (one), the MCU will jump to the corresponding Interrupt Vector. The flag is cleared when the interrupt routine is executed. Alternatively, the flag can be cleared by writing a logical one to it. • Bit 1 – PCIF1: Pin Change Interrupt Flag 1 When a logic change on any PCINT15:8 pin triggers an interrupt request, PCIF1 becomes set (one). If the I-bit in SREG and the PCIE1 bit in PCICR are set (one), the MCU will jump to the corresponding Interrupt Vector. The flag is cleared when the interrupt routine is executed. Alternatively, the flag can be cleared by writing a logical one to it. • Bit 0 – PCIF0: Pin Change Interrupt Flag 0 When a logic change on any PCINT7:0 pin triggers an interrupt request, PCIF0 becomes set (one). If the I-bit in SREG and the PCIE0 bit in PCICR are set (one), the MCU will jump to the corresponding Interrupt Vector. The flag is cleared when the interrupt routine is executed. Alternatively, the flag can be cleared by writing a logical one to it. 15.2.7 PCMSK2 – Pin Change Mask Register 2 • Bit 7:0 – PCINT23:16: Pin Change Enable Mask 23:16 Each PCINT23:16-bit selects whether pin change interrupt is enabled on the corresponding I/O pin. If PCINT23:16 is set and the PCIE2 bit in PCICR is set, pin change interrupt is enabled on the corresponding I/O pin. If PCINT23:16 is cleared, pin change interrupt on the corresponding I/O pin is disabled. 15.2.8 PCMSK1 – Pin Change Mask Register 1 • Bit 7:0 – PCINT15:8: Pin Change Enable Mask 15:8 Each PCINT15:8-bit selects whether pin change interrupt is enabled on the corresponding I/O pin. If PCINT15:8 is set and the PCIE1 bit in PCICR is set, pin change interrupt is enabled on the corresponding I/O pin. If PCINT15:8 is cleared, pin change interrupt on the corresponding I/O pin is disabled. Bit 7 6543210 0x1B (0x3B) – – – – – PCIF2 PCIF1 PCIF0 PCIFR Read/Write RRRRR R/W R/W R/W Initial Value 0 0000000 Bit 7 6 5 43210 (0x6D) PCINT23 PCINT22 PCINT21 PCINT20 PCINT19 PCINT18 PCINT17 PCINT16 PCMSK2 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 00000 Bit 765 4321 0 (0x6C) PCINT15 PCINT14 PCINT13 PCINT12 PCINT11 PCINT10 PCINT9 PCINT8 PCMSK1 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 000 0000 0 |
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