LAN7430 datasheet(7/77 Pages) MICROCHIP

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 2018-2019 Microchip Technology Inc.

DS00002631D-page 7

LAN7430/LAN7431

1.3

Table 1-3 describes the register but attributes used throughout this document.

1.4

Reference Documents

IEEE 802.3TM-2015 IEEE Standard for Ethernet,

http://standards.ieee.org/about/get/802/802.3.html

IEEE 802.1DTM-2004 IEEE Standard for Local and Metropolitan Area Networks - Media Access Control (MAC)

Bridges,

http://standards.ieee.org/about/get/802/802.1.html

IEEE 802.1QTM-2014 IEEE Standard for Local and Metropolitan Area Networks - Bridges and Bridged Networks,

http://standards.ieee.org/about/get/802/802.1.html

IEEE 1149.1-2013 IEEE Standard for Test Access Port and Boundary-Scan Architecture,



https://standards.ieee.org/findstds/standard/1149.1-2013.html

IEEE 1588-2008 IEEE Standard for Precision Clock Synchronization Protocol for Networked Measurement and

Control Systems,

https://standards.ieee.org/findstds/standard/1588-2008.html

Reduced Gigabit Media Independent Interface (RGMII) Specification Version 2.0,



https://web.archive.org/web/20160303171328/http://www.hp.com/rnd/pdfs/RGMIIv2_0_final_hp.pdf

PCI Express

® Base Specification Revision 3.1a, https://pcisig.com/specifications

PCI Bus Power Management Interface Specification Revision 1.2,

https://pcisig.com/specifications

TABLE 1-3:

Read:

A register or bit with this attribute can be read.

Write:

A register or bit with this attribute can be written.

Read only:

Read only. Writes have no effect.

Write only:

If a register or bit is write-only, reads will return unspecified data.

W1S

Write One to Set:

Writing a one sets the value. Writing a zero has no effect.

W1C

Write One to Clear:

Writing a one clears the value. Writing a zero has no effect.

WAC

Write Anything to Clear:

Writing anything clears the value.

Read to Clear:

Contents is cleared after the read. Writes have no effect.

Latch Low:

Clear on read of register.

Latch High:

Clear on read of register.

Self-Clearing:

Contents is self-cleared after being set. Writes of zero have no effect.

Contents can be read.

RO/LH

Read Only, Latch High:

This mode is used by the Ethernet PHY registers. Bits with

this attribute will stay high until the bit is read. After it a read, the bit will remain high, but

will change to low if the condition that caused the bit to go high is removed. If the bit has

not been read the bit will remain high regardless of if its cause has been removed.

NALR

Not Affected by Lite Reset.

The state of NALR bits does not change on assertion of a

lite reset.

NASR

Not Affected by Software Reset.

The state of NASR bits does not change on asser-

tion of a software reset.

STKY

This field is “Sticky” in that it is neither initialized nor modified by hot reset or Function

Level Reset.

RESERVED

Reserved Field:

Reserved fields must be written with zeros, unless otherwise indi-

cated, to ensure future compatibility. The value of reserved bits is not guaranteed on a

read.

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