LAN7430 datasheet(44/77 Pages) MICROCHIP

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LAN7430/LAN7431

DS00002631D-page 44

 2018-2019 Microchip Technology Inc.

6.13.2

PCIe LINK STATES (LOW POWER SUB-STATES)

The link states are not visible to PCI-PM legacy compatible software and are either derived from the power management

D-states of the corresponding components connected to that Link or by ASPM protocols.

The PCIe specification describes the rules and conditions for entry and exit of the link states.

The device supports the following Link power management states:

L0 - Active state

In this state, the main power supplies, reference clocks and the devices internal PLL are active. The platform’s Vaux

may or may not be active.

All PCI Express transactions and other operations are enabled.

L0 support is required for both ASPM and PCI-PM compatible power management.

L0 is available while in D0. It is also temporarily used in D3hot for messages during this state.

L0s – A low resume latency, energy saving “standby” state

In this state, the main power supplies, reference clocks and the devices internal PLL are active. The platform’s Vaux

may or may not be active.

TLP and DLLP transmission is disabled for a Port whose Link is in Tx_L0s.

The Physical Layer provides mechanisms for quick transitions from this state to the L0 state. When common (distrib-

uted) reference clocks are used on both sides of a Link, the transition time from L0s to L0 is typically less than 100 Sym-

bol Times.

It is possible for the Transmit side of one component on a Link to be in L0s while the Transmit side of the other compo-

nent on the Link is in L0.

L0s is not applicable to PCI-PM compatible power management and is optionally used by ASPM power management.

L0s is only available while in D0.

L1 – Higher latency, lower power “standby” state

In this state, the main power supplies are active. Reference clocks must remain active during L1, except as permitted

by Clock Power Management (using CLKREQ#) and/or L1 PM Sub-states when enabled. The devices internal PLL is

active, based on the availability of the reference clock. The platform’s Vaux may or may not be active.

TLP and DLLP transmission is disabled for a Link in L1.

Two power management Messages provide support for the PCI-PM L1 state:

• PM_Enter_L1 (DLLP)

• PM_Request_Ack (DLLP)

The L1 state is entered whenever all Functions of a Downstream component on a given Link are programmed to a D-

state other than D0. It may also be optionally entered by ASPM power management while in the D0 state.

The PCIe specification describes the rules for entry and exit of the link states. Exit from L1 is initiated by an Upstream-

initiated transaction targeting a Downstream component, or by the Downstream component’s initiation of a transaction

heading Upstream. Transition from L1 to L0 is typically a few microseconds.

L1 support is required for PCI-PM compatible power management and is optionally used by ASPM.

L1 Clock Power Management

If L1 Sub-states (below) are not enabled, the reference clock may still be removed and the PLL turned off. This function

is controlled by the Enable Clock Power Management field in the PCIe Link Control configuration register. Software

must only set this field if the Clock Power Management bit of the Link Capabilities register is a 1.

L1 Clock PM and L1 Sub-states work orthogonal to each other. However, L1 Sub-states takes precedence over Clock

PM. This means that when the entry conditions for any L1 Sub-state are satisfied then the device executes the corre-

sponding L1 Substate protocol.

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