LAN7430 datasheet(32/77 Pages) MICROCHIP

32 / 77 page

LAN7430/LAN7431

DS00002631D-page 32

 2018-2019 Microchip Technology Inc.

6.1.4

TERMINATION CAPACITORS

The TX pins require series capacitors in the range of 100nF to 200nF.

6.1.5

BEACONING

The PHY supports the PCIe beaconing wake-up mechanism.

6.2

PCI Express Endpoint Controller (PCIe EP)

The device integrates a PCIe 3.1 Endpoint controller that includes the following common PCIe features:

• Split transaction, packet-based protocol

• Common flat address space for load/store access

- 32 and 64-bit memory address spaces

- I/O address space

- Configuration address space

• Transaction layer mechanism

• Credit-based flow control

• Various packet sizes and formats

• Reset and initialization

• Data integrity support

• Link layer retry for recovery following error detection

• 8b/10b encoding with running disparity

• In-band messaging

• Power management:

- Wake capability from D3cold state

- Compliant with ACPI, PCI-PM software model

- Active state power management

Additional functional features supported include:

• All non-optional features of the PCI Express Base 3.1 Specification

• The following optional features of the specification:

- Latency Tolerance Reporting (LTR)

- Completion Timeout Ranges

- Function Level Reset (FLR)

- L1 Substates (L1SS, L1.1SS, L1.2SS)

- Optimized Buffer Fill and Flush (OBFF)

- Readiness Notifications (RN)

- PCI Express Active State Power Management (ASPM)

- PCI Express Advanced Error Reporting (AER) with Multiple Header Logging

- Device Serial Number

- ECRC generation and checking

• x1 Gen1 Lane @ 2.5 GT/s

• Advanced Power and Clock Management

• Configurable Max_Payload_Size (128 bytes to 512 bytes)

• MSI and MSI-X with Per-Vector Masking (PVM)

• INTx Legacy interrupt emulation

• Type 0 Configuration space

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