LAN7430 datasheet(56/77 Pages) MICROCHIP

номер детали	LAN7430

подробное описание детали	Low Power PCIe to Gigabit Ethernet Controller with Integrated Ethernet MAC / PHY

PDF	77 Pages

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производитель	MICROCHIP [Microchip Technology]

домашняя страница	http://www.microchip.com

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56 / 77 page

LAN7430/LAN7431

DS00002631D-page 56

 2018-2019 Microchip Technology Inc.

7.6

AC Specifications

This section details the various AC timing specifications of the device.

7.6.1

EQUIVALENT TEST LOAD

Output timing specifications assume a 25pF equivalent test load, unless otherwise noted, as illustrated in Figure 7-1.

7.6.2

POWER SEQUENCE TIMING

This section details the device power sequencing requirements. The VDDVARIO, VDDVARIO_B, VDD_SW_IN,

VDD_REG_IN, VDD_OTP, AVDDH_1 and AVDDH_2 power supplies must all reach operational levels within the spec-

ified time period tpon, as shown in Figure 7-2. When operating with the internal regulators disabled, VDD12CORE,

AVDD12, AVDDL_1, AVDDL_2, VPH, VPTX and VP are also included in this requirement, as shown in Figure 7-3.

In addition, all of the power supplies must reach 80% of their operating voltage level within 15ms. This requirement can

be safely ignored if using an external reset as shown in Section 7.6.4.

Device power supplies can turn off in any order provided they all reach 0 volts within the specified time period tpoff.

Note:

The MII timing adheres to or exceeds the IEEE 802.3 specification. Refer to the IEEE 802.3 specification

for additional MII timing information.

Note:

The RGMII timing adheres to or exceeds the HP RGMII Specification Version 2.0. Refer to this specification

for additional RGMII timing information.

FIGURE 7-1:

OUTPUT EQUIVALENT TEST LOAD

FIGURE 7-2:

POWER SEQUENCE TIMING (INTERNAL REGULATORS)

25 pF

OUTPUT

VDDVARIO,

VDDVARIO_B

VDD_SW_IN, VDD_REG_IN,

VDD_OTP, AVDDH_1, AVDDH_2

tpon

tpoff

LAN7430 датащи(PDF) 56 Page - Microchip Technology